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A built-in self-test technique that is applicable to symmetric
microsystems is described. A combination of existing layout
features and additional circuitry is used to make measurements
from symmetrically-located points. In addition to the
normal sense output, self-test outputs are used to detect the
presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal
that our self-test approach is able to distinguish misbehavior
resulting from local defects and global manufacturing
process variations. A mathematical model is developed to analyze
the efficacy of the differential built-in self-test method
in characterization of a wide range of local manufacturing
variations affecting different regions of a device and/or wafer.
Model predictions are validated by simulation. Specifically, it
has been shown that by using a suitable modulation scheme,
sensitivity to etch variation along a particular direction is improved
by nearly 30%.
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