 |
An optimal layout synthesis methodology for CMOS MEMS accelerometers is presented. It consists of a parametrized layout generator that optimizes design objectives while meeting functional specifications. The behavior of the device is estimated using lumped parameter analytical equations. The design problem is then formulated into a non-linear constrained optimization problem. Such an approach to automated design of MEMS devices helps the designer to explore design trade-offs efficiently. Synthesis of cell level devices is also required for structured design of integrated MEMS. Designs for a CMOS MEMS accelerometer for different optimization objectives, as well as possible design trade-offs are discussed.
|
|
© 2000 Computational Publications. Abstracting is permitted with credit to the source. Other copying, reprint or repoduction requests should be addressed to: Copyrights Manager, Computational Publications, Copyright Office, 899 Rue Jean de Gingins, 01220 Divonne les Bains, France. Computational Publications is a subsuduary of the Applied Computational Researh Society, a non-profit organization
|
|
Full paper not available from outside CMU
|
