CMU MEMS Laboratory Publication Abstract


in IEEE/ASME Journal of Microelectromechanical Systems, Volume 11, Issue 2, pp. 93-101, April 2002.
Post-CMOS Processing for High-Aspect-Ratio Integrated Silicon Microstructures
H. Xie, L. Erdmann, X. Zhu, K. Gabriel and G. Fedder
We present a new fabrication sequence for integrated- silicon microstructures designed and manufactured in a conventional complentary metal–oxide–semiconductor (CMOS) process. The sequence employs a post-CMOS deep silicon backside etch, which allows fabrication of high aspect ratio (25:1) and flat (greater than 10 mm radius of curvature) MEMS devices with integrated circuitry. A comb-drive resonator, a cantilever beam array and a z-axis accelerometer were fabricated using this process sequence. Electrical isolation of single-crystal silicon was realized by using the undercut of the reactive ion etch (RIE) process. Measured out-of-plane curling across a 120-µm-wide 25-µm-thick silicon released plate was 0.15 m, which is about ten times smaller than curl of the identical design as a thin-film CMOS microstructure. The z-axis DRIE accelerometer structure is 0.4 mm by 0.5 mm in size and has a 25-µm-thick single-crystal silicon proof mass. The measured noise floor is 1 mG/√Hz, limited by electronic noise. A vertical electrostatic spring "hardening" effect was theoretically predicted and experimentally verified.
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Full paper (PDF) (opens in new window).

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