CMU MEMS Laboratory Publication Abstract


in Technical Proceedings of the Sixth International Conference on Modeling and Simulation of Microsystems Semiconductors, Sensors and Actuators (MSM), pp. 262-265, February 24-26, 2003, San Francisco, California.
Layout Verification by Extraction for Micro Total Analysis Systems
B. Baidya and T. Mukherjee
The increasing complexity of MicroTotalAnalysis Systems is leading to a growing need for verification tools for such designs. Numerical simulation of such designs are slow, memory consuming and practically impossible for large designs. Schematic-based simulation have been shown to be more efficient in capturing the behavior of such designs. However, currently such schematics need to be manually constructed from rather complex layouts, leaving them prone to human errors. This paper presents a prototype implementation of a mu-TAS layout extractor capable of reconstructing an extracted schematic, from any given mu-TAS layout, which can then be simulated using schematic models. The paper discusses the algorithms necessary for the extractor and also presents some results demonstrating the usefulness of such a tool.
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