CMU MEMS Laboratory Publication Abstract

 

in Technical Proceedings of the Fourth International Conference on Modeling and Simulation of Microsystems (MSM), pp. 426-429, March 19-21, 2001, Hilton Head, SC, USA.
Layout Verification and Correction of CMOS-MEMS Layouts
B. Baidya, K. He and T. Mukherjee
ABSTRACT:
The advent of CMOS micromachining has introduced new design rules for fabrication of integrated CMOS-MEMS devices. This paper presents a context dependent DRC algorithm to handle the issues related to prefabrication verification of such layouts. In addition, problems related to density control, specific to CMOS-MEMS designs, are discussed. An automatic slotter which introduces MEMS-compatible slot holes is presented and its capability demonstrated. Having such verification and correction tools which address the needs of integrated CMOS-MEMS designs will help reduce integrated MEMS design time.
© 2001 Computational Publications. Abstracting is permitted with credit to the source. Other copying, reprint or repoduction requests should be addressed to: Copyrights Manager, Computational Publications, Copyright Office, 899 Rue Jean de Gingins, 01220 Divonne les Bains, France. Computational Publications is a subsuduary of the Applied Computational Researh Society, a non-profit organization
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