Methodology Process Simulation CODEF creates defect by simulating contamination during wafer process. CODEF may be executed in "Monte-Carlo mode", in which simulations are repeated, each with a different set of contamination parameters. CODEF takes three input files, process description, layout and contamination parameters. The layout masks of CODEF is required in Caltech Intermediate Form (CIF). In the case of Monte-Carlo mode, CODEF requires an extra input, the contamination parameters, information containing contamination statistics of each process step.   Post-Simulation Anlysis For a single simulation, CODEF performs a process simulation and outputs a netlist in Spice and Gemini-II format. In Monte-Carlo mode, 10,000 simulations are usually required. The netlists are then simulated to obtain the electrical behaviors of the defects. The electric behaviors are than analyzed to determine their fault modes. This post-simulation task, if done by hand, can be over-whelmingly energy and time consuming. Thus, a tool called Fault Analysis Tool (FAT) was developed to automate this process. The main features of FAT version 2.0 include: Netlist Comparison - FAT invokes GeminiII (netlist comparison program) to identify unique netlists for circuit simulation. SPICE Stimuli - FAT can create exhaustive test patterns to test for functional or transitional faults. Automated SPICE simulation - FAT is able to invoke SPICE to simulate the selected netlists and record the results. Fault Analysis - FAT groups the netlists with same fault behaviors as shown below. Fault to Contamination Mapping - For each Unique fault, FAT provides characteristic of the contamination.  In_a In_b Out  0  0  0  1  0  0  0  1  0  1  1  0 3/21 = .76 % step = metal1.dev #70 diam = 1.0911 um, x,y=(341.891,8117.816) run=1 step= tub_diffuse #10 diam=1.09424 um, x,y=(323.571,402.889) run=3 step= etch_n_res #12 diam=1.2485 um, x,y=(181.565,470.787) run=5
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