Stack Computers: the new wave © Copyright 1989, Philip Koopman, All Rights Reserved.
Chapter 2. A Taxonomy of Hardware Stack Support
In order to convey the category for a particular architecture, we shall use a three character shorthand notation based on the three axes of classification. The first letter of the abbreviation specifies the number of stacks (Single or Multiple). The second letter of the abbreviation specifies the size of dedicated stack memory (Small or Large). The third letter of the abbreviation specifies the number of operands in the instruction format (0, 1, or 2). Thus, the abbreviation SS0 would signify an architecture with a single stack, small dedicated stack memory, and 0-operand addressing and the abbreviation ML2 would signify an architecture with multiple stacks, large dedicated stack memory, and 2-operand addressing.
Table 2.1 shows the categorization of existing and historical stack oriented architectures by taxonomy category. Appendix A briefly discusses each of these architectures and how they implement features related to the taxonomy.
Category Machines SS0 Aerospace Computer, Burroughs family, Caltech Chip, EULER, GLOSS, HITAC-10, ITS, LAX2, Mesa, Microdata 32/S, Transputer, WD9000 SS1 AAMP, Buffalo Stack Machine, EM-1, HP300/HP3000, ICL2900, IPL-VI, MCODE, MU5, POMP Pascal SS2 Intel 80x86 SL0 G Machine, NORMA SL1 AADC, Micro-3L SL2 AM29000, CRISP, Dragon, Pyramid 90x, RISC I, SOAR MS0 Action Processor, APL Language Machine, FORTRAN Machine, HUT, Internal Machine, MISC M17, Rockwell Microcontrollers, Symbol, Tree Machine MS1 PDP-11 MS2 Motorola 680x0 ML0 ALCOR, An ALGOL Machine, FRISC 3, KDF-9, Kobe University Machine, MF1600, NC4016, OPA, PASCAL Machine, QFORTH, Reduction Language Machine, Rekursive, RTX 2000, RTX 32P, RUFOR, The Forth Engine, TM, Vaughan & Smith's Machine, WISC CPU/16, WISC CPU/32 ML1 Lilith, LISP machines, SF1, Soviet Machine ML2 PSP, SF1, Socrates
Table 2.1. Population of the stack machine taxonomy
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