Philip J. Koopman, Jr
Draft text for article published in:
Embedded Systems Programming, 6(5), May 1993, pp. 26-34
(For a nicely typeset and edited version, please refer to that published article.)
While the cache memory designed into advanced processors can significantly speed up the average performance of many programs, it also causes performance varations that surprise system designers and cause problems during product integration and deployment. This paper gives a description of cache memory behavior for real-time embedded systems, using the example of real data collected from an 80486 CPU interrupt service routine. While vendor-supported tools for predicting and bounding worst-case CPU delays are still in their infancy, there are some coping strategies that will reduce problems while minimizing risk.
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Phil Koopman -- firstname.lastname@example.org