FPGA Prototyping and Emulation of Computer Systems
From James Hoe
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| This research explores the application of Field Programmable Gate Arrays (FPGA) and High-level Hardware Synthesis technologies in computer systems prototyping and emulation. This research is currently supported in funding and/or equipment by NSF, FCRP/C2S2, SUN, and Xilinx. Please see the [http://www.ece.cmu.edu/~protoflex/ ProtoFlex] project page for complete and up-to-date details. Please also visit the related [http://www.ece.cmu.edu/~simflex/ SimFlex] project on multiprocessor simulation (in software). My students and I are members of the multi-university [http://ramp.eecs.berkeley.edu RAMP] project. | This research explores the application of Field Programmable Gate Arrays (FPGA) and High-level Hardware Synthesis technologies in computer systems prototyping and emulation. This research is currently supported in funding and/or equipment by NSF, FCRP/C2S2, SUN, and Xilinx. Please see the [http://www.ece.cmu.edu/~protoflex/ ProtoFlex] project page for complete and up-to-date details. Please also visit the related [http://www.ece.cmu.edu/~simflex/ SimFlex] project on multiprocessor simulation (in software). My students and I are members of the multi-university [http://ramp.eecs.berkeley.edu RAMP] project. | ||
| - | * '''Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation'''. Eric S. Chung, [[James C. Hoe]]. Formal Methods and Models for Codesign (MEMOCODE), July 2009. ([http://www.ece.cmu.edu/~jhoe/distribution/2009/mc09.pdf pdf]) | + | * '''Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation'''. E. S. Chung, J. C. Hoe. Formal Methods and Models for Codesign (MEMOCODE), July 2009. ([http://www.ece.cmu.edu/~jhoe/distribution/2009/mc09.pdf pdf]) |
| - | * '''ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs'''. Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, [[James C. Hoe]], Babak Falsafi and Ken Mai. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2, June 2009. ([http://portal.acm.org/ft_gateway.cfm?id=1534925&type=pdf&coll=portal&dl=ACM&CFID=40239650&CFTOKEN=89804458 pdf]) ''(This is the full journal version of the FPGA 2008 paper.)'' | + | * '''ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs'''. E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2, June 2009. ([http://portal.acm.org/ft_gateway.cfm?id=1534925&type=pdf&coll=portal&dl=ACM&CFID=40239650&CFTOK.=89804458 pdf]) ''(This is the full journal version of the FPGA 2008 paper.)'' |
| - | * '''A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs'''. Eric S. Chung, Eriko Nurvitadhi, [[James C. Hoe]], Babak Falsafi and Ken Mai. International Symposium on Field Programmable Gate Arrays (FPGA), February 2008. ([http://www.ece.cmu.edu/~jhoe/distribution/2008/fpga08.pdf pdf]) | + | * '''A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs'''. E. S. Chung, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. International Symposium on Field Programmable Gate Arrays (FPGA), February 2008. ([http://www.ece.cmu.edu/~jhoe/distribution/2008/fpga08.pdf pdf]) |
| - | * '''RAMP: A Research Accelerator for Multiple Processors'''. John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, [[James C. Hoe]], Derek Chiou, Krste Asanovic. IEEE Micro, Volume 27, Number 2 , March/April 2007. ([http://ieeexplore.ieee.org/iel5/40/4287384/04287395.pdf?tp=&arnumber=4287395&isnumber=4287384 pdf]) | + | * '''RAMP: A Research Accelerator for Multiple Processors'''. J. Wawrzynek, D. A. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, K. Asanovic. IEEE Micro, Volume 27, Number 2 , March/April 2007. ([http://ieeexplore.ieee.org/iel5/40/4287384/04287395.pdf?tp=&arnumber=4287395&isnumber=4287384 pdf]) |
| - | * '''RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform'''. Arvind, Krste Asanovic, Derek Chiou, [[James C. Hoe]], Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, David Patterson, Jan Rabaey, John Wawrzynek. September 2005. ([http://www.ece.cmu.edu/~jhoe/distribution/2005/ramp-nsf2005.pdf pdf]) ''(note: this is the tech report version of the original 2005 NSF proposal on RAMP.)'' | + | * '''RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform'''. Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.-L. Lu, M. Oskin, D. Patterson, J. Rabaey, J. Wawrzynek. September 2005. ([http://www.ece.cmu.edu/~jhoe/distribution/2005/ramp-nsf2005.pdf pdf]) ''(note: this is the tech report version of the original 2005 NSF proposal on RAMP.)'' |
| - | * '''In-System FPGA Prototyping of an Itanium Microarchitecture'''. Roland Wunderlich and [[James C. Hoe]]. International Conference on Computer Design (ICCD), October 2004. ([http://www.ece.cmu.edu/~jhoe/distribution/2004/iccd04.pdf pdf]) | + | * '''In-System FPGA Prototyping of an Itanium Microarchitecture'''. R. Wunderlich and J. C. Hoe. International Conference on Computer Design (ICCD), October 2004. ([http://www.ece.cmu.edu/~jhoe/distribution/2004/iccd04.pdf pdf]) |
| - | * '''High-Level Modeling and FPGA Prototyping of Microprocessors'''. Joydeep Ray and [[James C. Hoe]]. International Symposium on Field Programmable Gate Arrays (FPGA), February 2003. ([http://www.ece.cmu.edu/~jhoe/distribution/2003/fpga03.pdf pdf]) | + | * '''High-Level Modeling and FPGA Prototyping of Microprocessors'''. J. Ray and J. C. Hoe. International Symposium on Field Programmable Gate Arrays (FPGA), February 2003. ([http://www.ece.cmu.edu/~jhoe/distribution/2003/fpga03.pdf pdf]) |
| [[Category: Research Areas]] | [[Category: Research Areas]] | ||
Current revision
This research explores the application of Field Programmable Gate Arrays (FPGA) and High-level Hardware Synthesis technologies in computer systems prototyping and emulation. This research is currently supported in funding and/or equipment by NSF, FCRP/C2S2, SUN, and Xilinx. Please see the ProtoFlex project page for complete and up-to-date details. Please also visit the related SimFlex project on multiprocessor simulation (in software). My students and I are members of the multi-university RAMP project.
- Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation. E. S. Chung, J. C. Hoe. Formal Methods and Models for Codesign (MEMOCODE), July 2009. (pdf)
- ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2, June 2009. (pdf) (This is the full journal version of the FPGA 2008 paper.)
- A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs. E. S. Chung, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. International Symposium on Field Programmable Gate Arrays (FPGA), February 2008. (pdf)
- RAMP: A Research Accelerator for Multiple Processors. J. Wawrzynek, D. A. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, K. Asanovic. IEEE Micro, Volume 27, Number 2 , March/April 2007. (pdf)
- RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform. Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.-L. Lu, M. Oskin, D. Patterson, J. Rabaey, J. Wawrzynek. September 2005. (pdf) (note: this is the tech report version of the original 2005 NSF proposal on RAMP.)
- In-System FPGA Prototyping of an Itanium Microarchitecture. R. Wunderlich and J. C. Hoe. International Conference on Computer Design (ICCD), October 2004. (pdf)
- High-Level Modeling and FPGA Prototyping of Microprocessors. J. Ray and J. C. Hoe. International Symposium on Field Programmable Gate Arrays (FPGA), February 2003. (pdf)
