Digital Signal Processing Hardware

From James Hoe

This research develops a domain-specific hardware synthesis framework for digital signal processing (DSP) computations. By incorporating domain-specific knowledge of mathematics and algebra into a synthesis tool, the proposed framework can manipulate a math-level transform description to optimize a DSP transform implementation at the algorithmic and architectural design level. This research is a part of the SPIRAL project. This research is in part supported by NSF through an ITR Award and by DARPA through the DESA program.

• Real Time Stereo Vision Using Exponential Step Cost Aggregation on GPU. W. Yu, T. Chen, J. C. Hoe. International Conference on Image Processing (ICIP), November 2009.

• Real-Time FPGA-Based 21.4GS/s Optical OFDM Transmitter. Y. Benlachtar, P. M. Watts, R. Bouziane, P. A. Milder, D. Rangaraj, A. Cartolano, R. Koutsoyannis, J. C. Hoe, M. Püschel and R. I. Killey. Optics Express, Volume 17, Issue 20, pp.17658-17668, September 2009.

• 21.4 GS/s Real-Time DSP-Based Optical OFDM Signal Generation and Transmission Over 1600 km of Uncompensated Fibre. Y. Benlachtar, P. M. Watts, R. Bouziane, P. Milder, R. Koutsoyannis, J. C. Hoe, M. Püschel, M. Glick and R. I. Killey. European Conference and Exhibition on Optical Communication Conference, September 2009. (Post Deadline Session)

• Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations. P. A. Milder, J. C. Hoe and M. Pueschel. Design, Automation and Test in Europe (DATE), April 2009. (pdf)

• Permuting Streaming Data Using RAMs. M. Pueschel, P. A. Milder and J. C. Hoe. Journal of the ACM (JACM), Volume 56 , Issue 2, April 2009. (pdf)

• Formal Datapath Representation and Manipulation for Implementing DSP Transforms. P. A. Milder, F. Franchetti, J. C. Hoe, M. Pueschel. Design Automation Conference (DAC), June 2008. (pdf)

• Time-Multiplexed Multiple Constant Multiplication. P. Tummeltshammer, J. C. Hoe, and M. Pueschel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 26, Number 9, September 2007. (pdf)

• Generating FPGA-Accelerated DFT Libraries. P. D'Alberto, F. Franchetti, P. A. Milder, A. Sandryhaila, J. C. Hoe, J. Johnson, J. M. F. Moura and M. Pueschel. Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2007. (pdf)

• Discrete Fourier Transform Compiler: From Mathematical Representation to Efficient Hardware. P. A. Milder, F. Franchetti, J. C. Hoe, and M. Pueschel. CSSI Technical Report, No. CSSI 07-01, January 2007. (pdf)

• Spiral: Joint Runtime and Energy Optimization of Linear Transforms. M. Telgarsky, J. C. Hoe, and J. Moura. International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2006. (pdf)

• Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores. P. Milder, M. Ahmad, J. C. Hoe, and M. Pueschel. International Symposium on Field Programmable Gate Arrays (FPGA), February 2006. [(pdf and try out the tool dftgen)

• Automatic Generation of Customized Discrete Fourier Transform IPs. G. Nordin, P. Milder, J. C. Hoe, and M. Pueschel. Design Automation Conference (DAC), June 2005. (pdf and try out the tool dftgen)

• Custom Optimized Multiplierless Implementations of DSP Algorithms. M. Pueschel, A. Zelinski, and J. C. Hoe. International Conference on Computer Aided Design (ICCAD), November 2004. (pdf)

• Multiple Constant Multiplication by Time Multiplexed Mapping of Addition Chains. P. Tummeltshammer, J. C. Hoe, and M. Pueschel. Design Automation Conference (DAC), June 2004. (pdf)

• Automatic Cost Minimization for Multiplierless Implementations of Discrete Signal Transforms. A. Zelinski, M. Pueschel, S. Misra, and J. C. Hoe. International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2004. (pdf)