Herman Schmit, PhD
C ONTACT: 
Office  Residence 
Hamerschlag Hall 2108 
Dept. of Electrical and Computer Engineering 
Carnegie Mellon University 
5000 Forbes Ave 
Pittsburgh, PA  15213		 5341 Beeler St. 
Pittsburgh, PA  15217
Phone: (412) 268-6470 
FAX: (412) 268-3204		 Phone: (412) 688-0998
Email Address : herman@ece.cmu.edu
URL:  http://www.ece.cmu.edu/~herman
 
RESEARCH:  My research is driven by three important trends in digital technologies:
  • The continued exponential scaling of silicon technology, which makes billions of transistors available to users, but which also requires engineering productivity to keep pace.
  • The transition of computing workloads from data-centric to media centric.
  • The escalating cost of chip fabrication plants and the high NRE of chips, which makes it necessary to maximize the market of single components, minimize design risk, and allow for post-fabrication modification to circuits.

The computing industry must adapt to these new trends to continue to prosper. Future digital systems must efficiently exploit the massive numbers of transistors on chips for computing workloads, but must simultaneously be more widely applicable, simply because fewer unique chips will be manufactured in the future. For these reasons, I believe post-fabrication configuration and customization of digital hardware will become increasingly important. Post-fabrication configuration allows developers to create specialized applications with commodity hardware. With post-fabrication configuration of hardware, fewer chips can be manufactured, while satisfying the market demand for differentiated products.

Post-fabrication customization of digital hardware happens in many ways today. One example is the microprocessor, where an instruction stream modifies the sequential behavior of the hardware to perform applications that the hardware developers could not have created or even imagined. Microprocessors, I believe, will eventually be limited by the paradigm of the serial instruction stream, because of the high cost and complexity of hardware to do run-time parallelization necessary in order to exploit a billion transistor chip.

Field-programmable gate arrays (FPGAs) and similar devices have static configuration streams, which can modify the device's behavior at power up. These configuration streams can be thought of as extremely wide, static instructions. While this programming paradigm allows for the exploitation of massive parallelism, it is also limited by the static, constrained nature of its instruction. FPGA instructions can not be easily ported to newer, larger chips, and cannot be emulated on smaller, cheaper chips.

The primary focus of my research has been to develop techniques for enabling the exploitation of massive parallelism through reconfigurable computing, as demonstrated by FPGA-computing, while simultaneously supporting some important features familiar to software developers, such as virtualization, forward-compatibility, and design re-usability. Towards that end, my students and I have developed PipeRench, which is a scalable, forward-compatible architecture for reconfigurable computing. My students have designed the architecture, including a detailed simulation model, an applications program interface, and are currently finishing the design of a large-scale implementation of the architecture in 0.35 micron silicon. In co-operation with Seth Copen Goldstein of the Computer Science Department, we have developed a compiler for this architecture, and have shown performance benefits of 10x to 50x on media-centric computational tasks in the domain of signal processing, image recognition, and cryptography.

Good research in this field requires significant breadth of expertise, because one must understand hardware realities, compiler and architectural challenges, and applications issues. I consider myself a cross-disciplinary researcher between two of the sub-disciplines in computer engineering: computer architecture and electronic design automation. I am conversant in many application domains, including signal and image processing, cryptography, and communications.

In coming years, my students and I will focus on the scalability issues for reconfigurable computing architectures. Intellectually, I want to pursue a greater understanding of the relationship between reconfigurable architectures, such as PipeRench, and conventional processor architecture. The lack of understanding of this relationship has limited the dialogue between these two research fields. I also plan to more explore the application of reconfigurability within the context of traditional ASICs.

EXPERIENCE:  Associate Professor, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 
July 2002 - present 

Assistant Professor, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 
June 1998 - June 2002 

Research Engineer, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 
November 1995 - May 1998 
 
  • Principle Investigator, Digital Sandbox Project, January 2002 - Present
  • Principle Investigator, Cached Virtual Hardware Project , September 1996 - March 2002
      • Project Objectives: 
      • To create architectures, tools, and methodologies for the virtualization of hardware design.
      • To provide forward-compatibility to FPGAs.
      • To reduce FPGA configuration times by a factor of one thousand and provide simultaneous configuration and execution.
      • To demonstrate significant and scalable performance improvements on applications in the domains of signal processing, image processing and recognition, and cryptography.
      Responsibilities: 
      • Primary Proposal author.
      • Technical Leadership
      • Reporting and Administration
  • Project Coordinator, QuadRail Low Power Digital Design Project, November 1995-1999
      • Project Objective: 
      • To create specialized circuits and CAD techniques for the minimization of power dissipation in digital circuits.
      Responsibilities: 
      • Technical Organization
      • Reporting and Administration

    Hardware Engineer, Data General Corporation , Westboro, MA 
    July 1987 - June 1990. 

    • Responsible for the design of the memory board of a high-end ECL minicomputer. 
    • Created, simulated and debugged two gate arrays. 
    • Evaluated technology and architectural options and fault tolerant memory. 
    • Developed error-correcting code for memory that could be distributed over four identical gate arrays in the data path. 
     SKILLS: 

    • Proficient with C++ and C, Unix, PC, Macintosh.
    • Experienced with hardware description languages including Verilog and VHDL.
    • Experienced with computer-aided design tools including tools for synthesis, placement, routing, layout, extraction, and timing verification. functional and fault simulation, test pattern generation, and timing verification.
    SERVICE: 
    • Design Automation Pavillion Panel Moderator: "Hybrid FPGAs", June 2002.
    • NSF Design Automation Proposal Review Panel, October, 2001.
    • Systems-on-a-Chip Cirriculum Task Force, Pittsburgh Digital Greenhouse. September 2000 - Present.
    • Review Board for Systems-on-a-Chip Education Program. Pittsburgh Digital Greenhouse. August 1999.
    • International Technology Roadmap for Semiconductors - Design Chapter Committee. November 2000 - November 2001.
    • NSF Design Automation Proposal Review Panel, January, 2000.
    • IEEE Transactions on VLSI Systems: Associate Editor (1999-2000)
    • IEEE/ACM International Symposium on Field Programmable Gate Arrays: 
      • Panel Session Organizer (1997,2000).
      • Technical Program Committee (1998-2002).
      • Publicity Chair (1999).
    • IEEE Symposium on FPGAs for Custom Computing Machines: 
      • Program Committee (1998-2002).
    • Reconfigurable Architectures Workshop: 
      • Program Committee (1998).
    EDUCATION:  Carnegie Mellon University , Pittsburgh, PA 
    PhD, Electrical and Computer Engineering (November 1995) 
    • Advisor: Prof. D. E. Thomas
    • Thesis: Synthesis of Application-Specific Memory Structures 

      • Synopsis: The mapping of values in a behavior to storage elements in an implementation of that behavior is critical in determining the final cost and performance of the implementation. Yet the problem of determining mapping of values to storage has never been fully addressed. In this thesis we develop a representation of this mapping which allows a wide range of trade-offs to be made. We show how this representation can be used by a design optimizer based on simulated annealing to automatically generate designs which meet user-specified goals. We demonstrate the effectiveness of this approach by synthesizing implementations of a fuzzy controller, a speech phoneme recognizer, and a digital signal processor and an image compressor. 
    • Research Assistant: September 1990 - October 1995
    University of Pennsylvania , Philadelphia, PA 
    BSE, Computer Science Engineering (May 1987), Cum Laude 
    • Grade Point: 3.65/4.0
    PUBLICATIONS: 
    Journal Articles
    • Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, R. Reed Taylor, "PipeRench: A Reconfigurable Architecture and Compiler," in Computer, April, 2000,   pdf

    • Herman Schmit, Seth Copen Goldstein, Srihari Cadambi, and Matthew Moe. "Pipeline Reconfigurable FPGAs," Journal of VLSI Signal Processing , March 2000, Kluwer Academic Publishers.

    • Herman Schmit and Donald E. Thomas, "Address Generation for Memories Containing Multiple Arrays," IEEE Transactions on CAD , vol.17, no.5, p. 377-385, May, 1998.   pdf   gzipped ps  

    • Herman Schmit and Donald E. Thomas, "Synthesis of Applications-Specific Memory Designs," IEEE Transactions on VLSI Systems,, Vol. 5, No. 1, pp. 101-111 March, 1997.

    • Donald E. Thomas, Jay Adams, and Herman Schmit, "A Model and Methodology for Hardware-Software Codesign," IEEE Design and Test of Computers, Vol. 10, No. 3, pp. 6-15, September, 1993.
    Archival Conference Papers
    • S. Chiricescu, M. Schuette, R. Gilton, and H. Schmit, "Morphable Multipliers," in 12th International Conference on Field Programmable Logic and Applications (FPL), 2002.   


    • D. Whelihan and H. Schmit, "Memory Optimization in Single Chip Network Switch Fabrics," in Proceedings of the Design Automation Conference (DAC), 2002,  pdf  


    • H. Schmit, D. Whelihan, A. Tsai, M. Moe, B. Levine, R. R. Taylor, "PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology," in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2002,    pdf


    • V. Chandra and H. Schmit, "Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA Using an Iso-Area Approach," in IEEE Computer Society International Symposium on VLSI (ISVLSI-02), April 2002.  pdf


    • H. Schmit, B. Levine, and B. Ylvisaker "Queue Machines: Hardware Compilation in Hardware," in IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), April 2002.   pdf


    • H. Schmit and V. Chandra, "FPGA Switch Block Layout and Evaluation," in IEEE/ACM International Symposium on Field Programmable Gate Arrays (FPGA-02), February 2002.  pdf


    • M. Moe and H. Schmit, "SCALIP - a scalable IP solution for pipelined arrays with limited feedback" Proceedings 14th Annual IEEE International ASIC/SOC Conference, 2001. Page(s): 334 -338, 2001. pdf


    • Y. Chou, P. Pillai, H. Schmit, and J. P. Shen, "PipeRench Implementation of the Instruction Path Coprocessor," in IEEE/ACM International Symposium on Microarchitecture (Micro-33), pp. 147-158, December 2000.  pdf


    • B. Levine, R. R. Taylor, H. Schmit, "Implementation of Near Shannon Limit Error-Correcting Codes using Reconfigurable Hardware" in FCCM 2000, 2000,   pdf

    • Bharath Ramasubramanian, Herman Schmit, L. Richard Carley, "Mixed-Swing QuadRail for Low Power Dual-Rail Domino Logic" in 1999 International Symposium on Low Power Electronics and Design. ISLPED 99 , 1999,   pdf

    • Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass, "Vertical Benchmarks for CAD" in DAC 99, 1999,   ps   pdf

    • Ron Laufer, R. Reed Taylor, Herman Schmit, "PCI-PipeRench and the SwordAPI: A System for Stream-based Reconfigurable Computing", in FCCM 99, 1999,   ps   pdf

    • Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer, "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," in International Symposium on Computer Architecture, pp. 38-49, 1999,   pdf   gzipped ps

    • Ram K. Krishnamurthy, Herman Schmit, L. Richard Carley, "A Low-power 16-bit Multiplier-Accumulator using Series-regulated Mixed Swing Techniques" in Proceedings IEEE Custom Integrated Circuits Conference , May 1998.  gzipped ps   pdf  

    • Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas, "Managing Pipeline-Reconfigurable FPGAs," Proceedings ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, p. 55-64, Feb. 1998.  ps   pdf  

    • Herman Schmit, "Incremental Reconfiguration for Pipelined Applications," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 47-55, 1997. ps   pdf

    • Herman Schmit and Donald E. Thomas, "Address Generation for Memories Containing Multiple Arrays," Proceedings of the International Conference on Computer Aided Design, ICCAD-95,, pp. 510-514, November, 1995. ps pdf

    • Herman Schmit and Donald E. Thomas, "Array Mapping in Behavioral Synthesis," Proceedings of the Eighth International Symposium on System Synthesis, pp. 90-95, September, 1995. ps pdf

    • Herman Schmit and Don Thomas, "Hidden Markov Modelling and Fuzzy Controllers in FPGAs," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 214-221, 1995. ps pdf

    • Herman Schmit, Lawrence Arnstein, Don Thomas, and Elizabeth Lagnese, "Behavioral Synthesis for FPGA-based Computing," Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, 1994.

    Conference/Symposium Papers (Full Paper Review)
    • Silviu Chiricescu, Michael Schuette, Robin Glinton, and Herman Schmit, "Morphable Multipliers," to appear in Field Programmable Logic and Applications (FPL), 2002.


    • Khosla, P., Schmit, H., Irwin, M.J., Vijaykrishnan, N., Cain, T., Levitan, S., Landis, D. "SoC design skills: collaboration builds a stronger SoC design team", Proceedings International Conference on Microelectronic Systems Education, 2001. Page(s): 42 -43, 2001. pdf


    • Ben Klass, Don Thomas, Herman Schmit, and David Nagle, "Modeling Inter-Instruction Energy Effects in a Digital Signal Processor," Power-Driven Microarchitecture Workshop, International Symposium on Computer Architecture , June, 1998. pdf  

    Book Chapters
    • Herman Schmit, Seth Copen Goldstein, Srihari Cadambi, and Matthew Moe. "Pipeline Reconfigurable FPGAs," in Field Programmable Custom Computing Technology: Architectures, Tools, and Applications, (Editors: Jeffrey Arnold, Wayne Luk, Kenneth Pocek), Kluwer Academic Publishers, 2000.
    Other Conference Papers
    • Benjamin Levine and Herman Schmit, "PipeRench: Power and Performance Evaluation of a Programmable Pipelined Datapath," in Hot Chips 14 Symposium, August 18-20, 2002.

    • R. D. (Shawn) Blanton, Seth Copen Goldstein, and Herman Schmit, "Tunable Fault Tolerance via Test and Reconfiguration," in Fault Tolerance Computing Symposium, 1998.  ps   pdf

    • Matthew Moe, Herman Schmit, and Seth Copen Goldstein, "Characterization and parameterization of a pipeline reconfigurable FPGA," in Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines, pp.294-5, April, 1998. 

    Theses
    • Herman Schmit, "Synthesis of Application-Specific Memory Structures," Ph.D. Thesis, Carnegie Mellon Universtiy,, November, 1995. gzipped ps

     PATENTS:  Awarded:
    • U.S. Patent No. 6,366,061: Multiple Power Supply Circuit Architecture Issued: April 2, 2002.
    • U.S. Patent No. 6,633,182:  Programmable gate array based on configurable metal interconnect vias Issued: October 14, 2003.
    Pending: 3
    CONSULTING: 


    • Heller Ehrman White McAuliffe, San Francisco CA. September 2000 - October 2001.
    • ST Microelectronics, Berkeley, CA. June 2000 - February 2001.
    • TVM, Technical Ventures Management, Boston MA. March 2000
    • Analog Devices, Norwood MA. August 1999.
    • Neolinear Corporation, Pittsburgh, Pennsylvania. May-August 1998.
    • Dasys Corporation, Pittsburgh, Pennsylvania. November 1995.
    PRESENTATIONS: 


    • PipeRench, Hybrid Machines and Queue Machines, Stanford University, August 21, 2002.
    • Constructive Fabrics: VPGAs, GSRC Review, New Orleans, LA, June 9, 2002.
    • Synthesis of Morphable Multiplier, International Workshop on Logic and Synthesis, New Orleans, LA, June 5, 2002.
    • Queue Machines: Hardware Compilation in Hardware, IEEE Symposium on FPGAs for Custom Computing Machines, Napa CA, April 2002.
    • Layout and Evaluation of FPGA Switch Blocks, ACM International Symposium on FPGAs, Monterrey, CA, February 2002.
    • Morphable Functional Units, Motorola Digital DNA Labs, Feb 15, 2002.
    • Deep, Wide and Hybrid: Architectures for High-ILP Cores, HP Labs and Sun Microsystems, July 12-13, 2001.
    • Regular, High-speed, Programmable Interconnect Components, GSRC Workshop, Las Vegas NV, June 2001.
    • Are Asynchronous Systems Inevitable?, GSRC Workshop, Las Vegas NV, June 2001.
    • PipeRench and XVM: SuperReconfigurableComputing, SRC Computers, Colorado Springs, March 2001.
    • Reconfigurable Computing Using Virtual Hardware, National Security Agency, February 1, 2001.
    • Reconfigurable Computing Using Virtual Hardware, Northrop Grumman, Baltimore, February 1, 2001.
    • Reconfigurable Computing Using Virtual Hardware, National Reconnaissance Office, February 2, 2001.
    • Domain Specific Virtual Hardware, Gigascale Research Center (GSRC), Review and Workshop, September 8, 2000.
    • Virtual Hardware, at ST Microelectronics, Crolles, France and Agrate, Italy, July 2000.
    • Cached Virtual Hardware Update, DARPA Adaptive Computing PI Meeting, Orlando FL, April 2000.
    • Reconfigurable Computing: Not Your Father's DSP, Analog Devices, September 10,1999.
    • Cached Virtual Hardware, DARPA PI Meeting, April 4, 1999.
    • PipeRench Architecture Summary, Lucent Technologies, December 14, 1998.
    • Vertical Benchmarks for Design Automation, ICCAD Birds-of-a-feather meeting on CAD Benchmarks, November 12, 1998.
    • FPGA Hardware Design Recipes, DARPA PI Meeting, October 1, 1998.
    • PipeRench: Motivation and Architecture, Imperial College, London, June 10, 1998.
    • Reconfigurable Computing: Not Your Father's x86, Princeton University, March 10, 1998.
    • Reconfigurable Computing: Not Your Father's x86, Purdue University, January 29, 1998.
    • The Million Gate FPGA? Lucent Technologies, July 11, 1997.
    • Cached Virtual Hardware for Configurable Computing, DARPA ACS PI Meeting, Berkeley, CA, June 23, 1997.
    • Incremental Reconfiguration for Pipelined Applications, IEEE Symposium on FPGAs for Custom Computing Machines, April 16, 1997.
    • Virtual Hardware for Reconfigurable Computing, Carnegie Mellon University, ECE Dept. Seminar, February 6, 1997.
    • Reconfiguration for FPGA-based Computing, National Semiconductor, Santa Clara, Nov. 1995.
    • Address Generation for Arrays Containing Multiple Arrays, International Conference on Computer-Aided Design (ICCAD-95), San Jose, CA, Nov. 1995.
    • Array Mapping in Behavioral Synthesis, International Symposium on System Synthesis, Cannes, France, Sept. 1995.
    • Hidden Markov Modeling and Fuzzy Controllers in FPGAs, IEEE Symposium on FPGAs Custom Computing Machines, Napa CA, April 1995.
    • FPGA-based Computing and Memory Synthesis, AT&T Bell Labs, Allentown, PA, February 1995.
    • Behavioral Synthesis for FPGA-based Computing, IEEE Workshop on FPGAs Custom Computing Machines, Napa CA, April 1994.
    GRANTS: 
    Awarded to Date:
    • Principal Investigator: "ITR: Spatial Computing Architectures", National Science Foundation, 36 months, $250,000.
    • Principal Investigator: "Dynamic, Low-Power, Via-Patterned Gate Arrays," Pittsburgh Digital Greenhouse, $296,880, July 15, 2002 - July 14, 2004.
    • Principal Investigator: "Digital Sandbox", Pittsburgh Digital Greenhouse, $1,300,000. Jan 1, 2002 - Dec 31, 2004.
    • Co-Principal Investigator: "Low Density Parity Check Code Implementations", NSIC, $80,000.
    • Co-Principal Investigator: "Seed Project for CSSI/IBM: Minimally Clocked Functional Unit Design," IBM, $80,000, June 1, 2001 - May 31, 2002.
    • Principal Investigator: "Tool Support for Morphable Functional Units," Motorola, $80,508, April 2001 - April 2002.
    • Principal Investigator: "Computing for Hyperspectral Imaginig," Northrop Grumman, Unrestricted Gift, $25,000.
    • Co-Principal Investigator: "Gigascale Research Center (GSRC): Center Proposal," SRC/MARCO/DARPA, January 2001- January 2004, $152,000.
    • Principal Investigator: "Reconfigurable Computing using Virtual Hardware," subcontract to Northrop Grumman (which had a contract with National Reconnaissance Office), December 1999- February 2001, $80,000.
    • Principal Investigator: "Demonstration Board for LDPC Prototyping." Chameleon Systems, Hardware Demonstration Board, approximate value $5,000, December 2000.
    • Co-Principal Investigator: "Configurable Systems-on-a-chip Design Methodologies with a Focus on Network Switching," Pittsburgh Digital Greenhouse, January 2000 - December 2001, $500,000.
    • Principal Investigator: "CAREER: Scalable Reconfigurable Computing," National Science Foundation, April 2000 - April 2004, $264,127.
    • Principal Investigator: "Instant Hardware: Contract Extension to Cached Virtual Hardware," DARPA, November 1999 - December 2001, $538,000.
    • Principal Investigator: "Vertical Benchmarks for Design Automation," SRC & IEEE-CAS: $45,000 unrestricted gift.
    • Principal Investigator: STMicroelectronics: "PipeRench for MPEG2," April 1999, $50,000 unrestricted gift.
    • Principal Investigator: DARPA contract entitled "Cached Virtual Hardware for Reconfigurable Computing," September 1996 - September 1999, $2,400,000.
    • Principal Investigator: Annapolis Micro Systems: Donation of three Wild-One boards. Approximate value: $10,000. Gift for use in research and education program.
    • Associate Faculty: DARPA contract entitled "Ultra-low energy per operation digital electronics," May 1995- September 1999, $1,800,000.

    Pending:
    • Co-Principal Investigator: "ECS: Context-Specifi Integrated Circuit with Sensors", National Science Foundation, 36 months, $500,000.