Books and Book Chapters

  • S. Garg, D. Marculescu, and R. Marculescu, “Fundamental Limits on Run-time Power Management Algorithms for MPSoCs,” in Sustainable and Green Computing Systems, P. Pande (ed.), Springer Verlag, 2013.
  • S. Herbert, D. Marculescu, “Variability-Aware Frequency Scaling in Multi-Clock Processors,” in Adaptive and Dynamic Techniques for Processor Optimization: Theory and Practice, A. Wang and S. Naffzinger (eds.), Springer Verlag, 2008.
  • E. Talpes, D. Marculescu, “Low power microarchitecture techniques,” in The VLSI Handbook, W.-K. Chen (ed.), CRC Book Press, 2006.
  • P. Stanley-Marbell, D. Marculescu, R. Marculescu, and P.K. Khosla, “Challenges and Opportunities in Modeling, Analysis and Optimization of Electronic Textiles,” in Low Power Electronics Design, C. Piguet (ed.), CRC Book Press, 2004.
  • P. Stanley-Marbell, N.H. Zamora, D. Marculescu, R. Marculescu, “Fault-tolerant techniques for ambient intelligent distributed systems,” in Ambient Intelligence: Impact on embedded-system design, T. Basten, M. Geilen, H. de Groot (eds.), Kluwer Academic Publishers, 2003.
  • V.S.P. Rapaka, D. Marculescu, “Efficient power/performance analysis of embedded and general purpose software applications,” in Embedded Software for SoC, A. Jerraya, S. Yoo, N. Wehn, D. Verkest (eds.), Kluwer Academic Publishers, 2003.
  • S.W. Haga, N. Reeves, R. Barua, D. Marculescu, “Dynamic functional units assignment for low power,” in Embedded Software for SoC, A. Jerraya, S. Yoo, N. Wehn, D. Verkest (eds.), Kluwer Academic Publishers, 2003.
  • D. Marculescu, R. Marculescu, “System and microarchitectural level power modeling, optimization, and their implications in energy aware computing,” in Power Aware Design Methodologies, M. Pedram, J. Rabaey (eds.), Kluwer Academic Publishers, 2002.
  • I. Athanasiu, D. (Raiciu) Marculescu, R. Sion, I. Mocanu, “Formal Languages – Applications,” Computer Science Department, “Politehnica” University of Bucharest Press, December 1999.

Journal Papers

Under Review

  • T.-Y. Ho, Y.-L. Chuang, Y.-W. Chang, D. Marculescu, “Pulsed-Latch Aware Placement and Clock-Network Co-Synthesis for Dynamic-Power Reduction,” under review, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, submitted 2012.

In press

  • D.-C. Juan, S. Garg, D. Marculescu, “Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip-Multiprocessors,” under review, ACM Trans. on Design Automation of Electronic Systems, submitted 2012.

2014

  • K.-C. Wu, D. Marculescu, “Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment,” in IEEE Trans. on Very Large Scale Integrated (VLSI) Circuits, vol.22, no.1, pp.136-145, Jan.2014.

2013

  • S. Garg, D. Marculescu, “Mitigating the Impact of Process Variations on the Performance 3D ICs,” in IEEE Trans. on Very Large Scale Integrated (VLSI) Circuits, vol.21, no.10, Oct.2013.
  • S. Garg, D. Marculescu, “Addressing Process Variations at the Microarchitecture and System Level,” in Foundations and Trends in EDA, vol.6, no.3, pp.217-291, April 2013.
  • K.-C. Wu, D. Marculescu, “A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits,” in press, IEEE Trans. on Very Large Scale Integrated (VLSI) Circuits, vol.21, no.2, pp.367-379, Feb.2013.

2012

  • S. Garg, D. Marculescu, “System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands,” in IEEE Trans. on Very Large Scale Integrated (VLSI) Circuits, vol.20, no.12, pp.2289-2310, Dec. 2012.
  • S. Garg, D. Marculescu, R. Marculescu, “Technology-driven Limits on Run-time Power Management Algorithms for Multi-processor Systems on Chip,” in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol.8, no.4, art.28, Oct.2012.
  • S. Herbert, S. Garg, D. Marculescu, “Exploiting Process Variability in Voltage/Frequency Control,” IEEE Trans. on Very Large Scale Integrated (VLSI) Circuits, vol.20, no.8, pp.1392-1404, Aug. 2012.
  • S. Garg, D. Marculescu, “On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks,” in ACM Trans. on Embedded Computing Systems, vol.11, no.2, art.33, July 2012.

2010

  • N. Miskov-Zivanov, D. Marculescu, “Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.10, pp.1614-1627, Oct. 2010.

2009

  • S. Herbert, D. Marculescu, “Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance,” in IEEE Trans. on VLSI Systems, vol.17, no.10, pp.1520-1533, Oct. 2009.
  • U.Y. Ogras, R. Marculescu, D. Marculescu, E.-G. Jung, “Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip,” in IEEE Trans. on VLSI Systems, vol.17, no.3, pp. 330-341, March 2009. (Special Section on Networks-on-Chip, Best Paper Award)
  • P. Choudhary, D. Marculescu, “Power Management of Voltage/Frequency Island-Based Systems Using Hardware Based Methods,” in IEEE Trans. on VLSI Systems, vol.17, no.3, pp. 427-438, March 2009.

2008

  • S. Garg, D. Marculescu, “System Level Throughput Analysis for Process Variation Adaptive Multiple Voltage-Frequency Island Designs,” in ACM Trans. on Design Automation of Electronic Systems, vol.13, No.4, pp. 1-25, Sept. 2008.
  • N. Miskov-Zivanov, D. Marculescu, “Modeling and Optimization for Soft Error Reliability of Sequential Circuits,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.27, No.5, pp. 803-816, May 2008.
  • D. Marculescu, S. Garg, “Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island, Latency-Constrained Systems,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.27, No.5, pp. 893-905, May 2008.

2007

  • U.Y. Ogras, R. Marculescu, H.G. Lee, P. Choudhary, D. Marculescu, M. Kaufman, P. Nelson, “Challenges and Promising Results in NoC Prototyping Using FPGAS,” in IEEE Micro, vol.27, No.5, Sept-Oct. 2007.
  • R.I. Bahar, D. Hammerstrom, J. Harlow, W.H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu, M. Pedram, “Architectures for Silicon Nanoelectronics and Beyond,” in IEEE Computer, vol. 40, No.1, pp.25-33, Jan. 2007.

2006

  • N. Miskov-Zivanov, D. Marculescu, “Circuit Reliability Analysis Using Symbolic Techniques,” in IEEE Trans. on Computer Aided Design of Integrated Circuits, Vol.25, No.12, pp.2638-2694, Dec. 2006.

2005

  • D. Marculescu, E. Talpes, “Energy Awareness and Uncertainty in Design at Microarchitecture Level,” in IEEE Micro, Vol.25, No.5, pp.64-76, September/October 2005. (Special Issue on Energy Efficient Design).
  • P. Koopman, H. Choset, R. Gandhi, B. Krogh, D. Marculescu, P. Narasimhan, J.M. Paul, R. Rajkumar, D. Siewiorek, A. Smailagic, P. Steenkiste, D.E. Thomas, C. Wang, “Undergraduate Embedded System Education at Carnegie Mellon,” in ACM Trans. on Embedded Computing Systems, vol.4, No.3, pp.500-528, August 2005. (Special Issue on Embedded Systems Education).
  • E. Talpes, D. Marculescu, “Toward a Multiple Clock/Voltage Island Design Style for Power Aware Processors,” in IEEE Trans. on VLSI Systems, vol.13, No.5, pp.591-603, May 2005.
  • S.W. Haga, N. Reeves, R. Barua, and D. Marculescu, “Dynamic Functional Unit Assignment for Low Power,” in Journal of Supercomputing, vol.31, No.1, pp. 47-62, Kluwer Academic Publishers, Jan. 2005.
  • E. Talpes, D. Marculescu, “Execution Cache Based Microarchitecture for Power Efficient Superscalar Processors,” in IEEE Trans. on VLSI Systems, vol.13, No.1, pp.14-26, Jan. 2005.

2003

  • D. Marculescu, R. Marculescu, N.H. Zamora, P. Stanley-Marbell, P.K. Khosla, S. Park, S. Jayaraman, S. Jung, C. Lauterbach, W. Weber, T. Kirstein, D. Cottet, J. Grzyb, G. Troester, “Electronic Textiles: A Platform for Pervasive Computing,” in Proceedings of IEEE, vol.91, No.12, Dec. 2003.
  • P. Stanley-Marbell, D. Marculescu, R. Marculescu, and P.K. Khosla, “Modeling, Analysis and Self-Management of Electronic Textiles,” in IEEE Trans. on Computers, vol.52, No.8, Aug. 2003. (Special issue on Wearable Computing).

2002

  • A. Iyer and D. Marculescu, “Microarchitecture-level Power Management,” in IEEE Trans. on VLSI Systems, vol.10, No.3, June 2002.

2000

  • D. Marculescu, R. Marculescu, and M. Pedram, “Theoretical Bounds for Switching Activity Analysis in Finite-State Machines”, in IEEE Trans. on VLSI Systems, vol.8, No.3, July 2000.
  • D. Marculescu, R. Marculescu, and M. Pedram, “Stochastic Sequential Machines Synthesis with Application to Constrained Sequence Generation,” in ACM Trans. on Design Automation of Electronic Systems, vol.5, No.2, Jan. 2000.

Conference, Symposia and Workshop Papers

2014

  • R. Kim, G. Liu, P. Wettin, R. Marculescu, D. Marculescu, P. P. Pande, “Energy-Efficient VFI-Partitioned Multicore Design Using Wireless NoC Architectures”, in Proc. International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES), New Delhi, India, Oct. 2014.
  • M. Shafique, S. Garg, D. Marculescu, J. Henkel, “ The EDA Challenges in the Dark Silicon Era,” in Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2014.
  • D.-C. Juan, L. Li, H.-K. Peng, D. Marculescu, C. Faloutsos, “Beyond Poisson: Modeling Inter-Arrival Times of Requests in a Datacenter,” in Proc. Pacific-Asia Conference on Knowledge Discovery and Data Mining (PAKDD), Tainan, Taiwan, May 2014.
  • Z. Qian, D.-C. Juan, P. Bogdan, C.-Y. Tsui, D. Marculescu, R. Marculescu, “A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis,” in Proc. IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan. 2014.

2013

  • G. Liu, J. Park, D. Marculescu, “Dynamic Thread Mapping for High-Performance, Power-Efficient Heterogeneous Manycore Systems,” in Proc. IEEE Intl. Conference on Computer Design (ICCD), Asheville, NC, Oct. 2013.
  • D.-C. Juan, S. Garg, J. Park, D. Marculescu, “Learning the Optimal Operating Point for Many-Core Systems with Extended Range Voltage/Frequency Scaling,” in Proc. ACM/IEEE Intl. Conference on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Montreal, Canada, Sept. 2013.
  • N. Miskov-Zivanov, D. Marculescu, J.R. Faeder, “Dynamic behavior of cell signaling networks: model design and analysis automation,” in Proc. ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2013. (Special session)
  • Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu, “HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors,” in Proc. ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2013.
  • D.-C. Juan, S. Garg, D. Marculescu, “Impact of Manufacturing Process Variations on Performance and Thermal Characteristics of 3D ICs: Emerging Challenges and New Solutions,” in Proc. IEEE Intl. Symposium on Circuits and Systems (ISCAS), Beijing, China, May 2013. (Invited Paper)
  • Z. Qian, D.-C. Juan, P. Bogdan, C.-Y. Tsui, D. Marculescu, R. Marculescu, “SVR-NoC: A Performance Analysis Tool for Network-on-Chip Architectures Using Learning-based Support Vector Regression Model,” in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013.
  • Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu, “Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors,” in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013.

2012

  • D.-C. Juan, D. Marculescu, “Power-aware Performance Increase via Core/Uncore Reinforcement Control for Chip-Multiprocessors,” in Proc. of ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Los Angeles, CA, Jul. 2012.
  • K.-C. Wu, D. Marculescu, M.-C. Lee, S.-C. Cheng, “Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms,” in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March 2012.
  • D.-C. Juan, Y.-L. Chuang, D. Marculescu, Y.-W. Chang, “Statistical Thermal Modeling and Mitigation Strategies Considering Leakage Power Variations,” in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March 2012.
  • M.-C. Lee, Y. Shi, Y.-G. Chen, D. Marculescu and S.-C. Chang, “Efficient On-line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs,” in ACM/IEEE Intl. Symposium on Physical Design (ISPD), Napa, CA, March 2012.
  • D.-C. Juan, H. Zhou, D. Marculescu, X. Li, “A Learning-Based Autoregressive Model for Fast Transient Thermal Analysis of Chip-Multiprocessors,” in Proc. IEEE/ACM Asia-South Pacific Design Automation Conference (ASPDAC), Sydney, Australia, Jan. 2012.

2011

  • Y. L. Chuang, T. Y. Ho, H. T. Lin, Y. W. Chang, D. Marculescu, “PRICE: Power Reduction by Placement and Clock-Network Co-Synthesis for Pulsed-Latch Designs,” in Proc. of the IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2011.
  • N. Miskov-Zivanov, A. Bresticker, S. Venkatakrishnan, P. Kashinkunti, D. Krishnaswamy, D. Marculescu, J. Faeder, “Regulatory Network Analysis Acceleration with Reconfigurable Hardware,” in Proc. Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Boston, MA, Sept. 2011.
  • K.-C. Wu, D. Marculescu, M.-C. Lee, and S.-C. Chang, “Analysis and Mitigation of NBTI-Induced Performance Degradation for Power-Gated Circuits,” in Proc. of ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, Aug. 2011.
  • N. Miskov-Zivanov, D. Krishnaswamy, S. Venkataraman, A. Bresticker, D. Marculescu, J.R. Faeder, “Emulation of Biological Networks in Reconfigurable Hardware,” in Proc. ACM Intl. Conference on Bioinformatics and Computational Biology (BCB), Chicago, IL, Aug. 2011.
  • S. Garg, D. Marculescu, “Parametric Yield and Reliability of 3D Integrated Circuits: New Challenges and Solutions,” in Proc. IEEE VLSI Test Symposium (VTS), Dana Point, CA, May 2011. (Invited paper)
  • D.-C. Juan, S. Garg, and D. Marculescu, “Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors In the Presence of Process Variations,” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011.
  • K.-C. Wu and D. Marculescu, “Aging-Aware Timing Analysis and Optimization Considering Path Sensitization,” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011.

2010

  • S. Garg, D. Marculescu, and S. Herbert, “Process Variation Aware Performance Modeling and Dynamic Power Management for Multicore Systems,” in IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2010. (Embedded tutorial)
  • S. Garg, D. Marculescu, and R. Marculescu, “Custom Feedback Control: Enabling Truly Scalable On-Chip Power Management for MPSoCs,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design, Austin, TX, Aug. 2010. PDF ACM Bibliometrics
  • D. Marculescu and N. Miskov-Zivanov, “Formal Modeling and Reasoning for Reliability Analysis,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2010. (Invited paper) PDF ACM Bibliometrics
  • S. Garg, R. Yan, R. Marculescu, D. Marculescu, and U. Schlichtmann, “Architectural Modeling of the Impact of Process Variations on Network-on-Chip Clock Frequency,” in Proc. Workshop on Diagnostic Services in Network-on-Chips (DSNOC), in conjunction with ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2010.
  • N. Miskov-Zivanov and D. Marculescu, “Modeling and Analysis of SER in Combinational Circuits,” in Proc. of IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), Stanford, CA, March 2010. (Invited paper)
  • K.-C. Wu and D. Marculescu, “Clock Skew Scheduling for Soft-Error-Tolerant Sequential Circuits,” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2010.

2009

  • A. Bonnoit, S. Herbert, D. Marculescu, and L. Pileggi, “Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection” in Proc. of IEEE/ACM Intl. Symposium on Low Power Electronics and Design (ISLPED), Aug. 2009. PDF ACM Bibliometrics
  • S. Garg, D. Marculescu, R. Marculescu, and U. Ogras, “Technology-driven Limits on DVFS Controllability of Multiple Voltage-Frequency Island Designs” in Proc. of IEEE/ACM Design Automation Conference (DAC), July 2009. PDF ACM Bibliometrics
  • K.-C. Wu and D. Marculescu, “Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, April 2009.
  • S. Garg and D. Marculescu, “Process Variability Analysis and Mitigation for 3D MPSoCs” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, April 2009.
  • S. Garg and D. Marculescu, “3D GCP - An Analytical Model for the Impact of Process Variations on the Critical Path Delay of 3D ICs” in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), March 2009. (Best Paper Award)
  • W.-P. Lee, Y.-W. Chang, and D. Marculescu , “Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-VoltageDesigns” in Proc. of IEEE/ACM International Symposium on Physical Design (ISPD), March 2009. PDF ACM Bibliometrics
  • S. Herbert and D. Marculescu, “Variation-Aware Dynamic Voltage/FrequencyScaling” in Proc. of the 15th International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2009.

2008

  • N. Miskov-Zivanov, K.-C. Wu, and D. Marculescu, “Process Variability-Aware Transient Fault Modeling and Analysis,” in Proc. ACM/IEEE Intl. Conference on Computer-Aided Design, San Jose, CA, Nov. 2008.
  • K.-C. Wu and D. Marculescu, “Power-Aware Soft Error Hardening via Selective Voltage Scaling,” in Proc. ACM/IEEE Intl. Conference on Computer Design, Lake Tahoe, CA, Oct. 2008. (Best Paper Award)
  • S. Garg and D. Marculescu, “System-Level Mitigation of WID Leakage Variations using Body-Bias Islands,” in Proc. ACM/IEEE Intl. Conference on Hardware-Software Codesign and Systems Synthesis (CODES+ISSS), Atlanta, GA, Oct. 2008. PDF ACM Bibliometrics
  • S. Herbert and D. Marculescu, “Characterizing Chip-Multiprocessor Variability-Tolerance,” in Proc. ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2008. (Paper nominated for Best Paper Award) PDF ACM Bibliometrics
  • U.Y. Ogras, R. Marculescu, and D. Marculescu, “Variation-Adaptive Feedback Control for Networks-on-Chip with Multiple Clock Domains,” in Proc. ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2008. (Paper nominated for Best Paper Award) PDF ACM Bibliometrics
  • N. Miskov-Zivanov, D. Marculescu, “A Systematic Approach to Modeling and Analysis of Transient Faults in Logic Circuits,” in Proc. IEEE Intl. Symposium on Quality on Electronic Design (ISQED), San Jose, CA, March 2008.
  • K.-C. Wu, D. Marculescu, “Soft Error Rate Reduction Using Redundancy Addition and Removal,” in Proc. IEEE/ACM Asia-South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan. 2008.

2007

  • S. Garg, D. Marculescu, “On the Impact of Manufacturing Process Variations On the Lifetime of Sensor Networks,” in Proc. ACM/IEEE Intl. Conference on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Salzburg, Austria, Sept. 2007 PDF ACM Bibliometrics
  • S. Herbert, D. Marculescu, “Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Portland, OR, Aug. 2007. PDF ACM Bibliometrics
  • U.Y. Ogras, R. Marculescu, P. Choudhary, D. Marculescu, “Voltage-Frequency Island Partitioning for GALS-Based Networks-on-Chip,” in Proc. ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 2007.(Paper nominated for Best Paper Award) PDF ACM Bibliometrics
  • S. Garg, D. Marculescu, System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs,” in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, Apr. 2007.
  • N. Miskov-Zivanov, D. Marculescu, “Soft Error Rate Analysis for Sequential Circuits,” in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, Apr. 2007.
  • P. Stanley-Marbell, D. Marculescu, ” An 0.9 X 1.2', Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface” in Proc. Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, Apr. 2007.
  • N.Miskov-Zivanov, D.Marculescu, “MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits,” in Proc. IEEE Intl. Symposium on Quality in Electronic Design (ISQED), San Jose, CA, March 2007. (Paper nominated for Best Paper Award)
  • P. Stanley-Marbell, D. Marculescu, “Sunflower: Full-System Embedded Microarchitecture Evaluation,” in Proc. Intl. Conf. on High Performance Embedded Architectures & Compilers (HiPEAC), Ghent, Belgium, Jan. 2007.

2006

  • D. Marculescu, S. Garg, “System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems,” in Proc. IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2006. PDF ACM Bibliometrics
  • S. Herbert, S. Garg, D. Marculescu, “Reclaiming Performance and Energy Efficiency from Variability,” in 4th Annual Thomas J. Watson P=ac2 Conference (PAC2), Yorktown, NY, Oct. 2006.
  • P. Choudhary, D. Marculescu, “Hardware based Frequency/Voltage Control of Voltage Frequency Island Systems,” in Proc. IEEE/ACM Intl. Conference on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Seoul, South Korea, Oct. 2006. PDF ACM Bibliometrics
  • P. Stanley-Marbell, D. Marculescu, “A Programming Model and Language Implementation for Concurrent Failure-Prone Hardware,” in Workshop on Programming Models for Ubiquitous Parallelism (PMUP), in conjunction with ACM/IEEE Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Seattle, WA, Sept. 2006
  • N. Miskov-Zivanov, D. Marculescu, “MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits,” in Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 2006. PDF ACM Bibliometrics
  • C.-H. Chang, D. Marculescu, “Design and Analysis of a Low Power VLIW DSP Core,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Karlsruhe, Germany, March 2006.

2005

  • K. Niyogi, D. Marculescu, “System Level Power and Performance Modeling of GALS Point-to-point Communication Interfaces,”in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), San Diego, CA, Aug. 2005. PDF ACM Bibliometrics
  • D. Marculescu, E. Talpes, “Variability and Energy Awareness: A Microarchitecture-Level Perspective,” in Proc. ACM/IEEE Design Automation Conference, (DAC), Anaheim, CA, June 2005. PDF ACM Bibliometrics
  • E. Talpes, D. Marculescu, “Increased Scalability and Power Efficiency through Multiple Speed Pipelines,” in Proc. ACM Intl. Symposium on Computer Architecture (ISCA), Madison, WI, June 2005. PDF ACM Bibliometrics
  • D. Marculescu, “Energy Bounds for Fault-Tolerant Nanoscale Designs,” in Proc. IEEE Design, Automation and Test in Europe, (DATE), Munich, Germany, February 2005. (Paper Nominated for Best Paper Award)
  • K. Niyogi, D. Marculescu, “Speed and Voltage Selection for GALS Systems Based on Voltage/Frequency Islands,” in Proc. ACM/IEEE Asian-South Pacific Design Automation Conference (ASPDAC), Shanghai, China, Jan. 2005. (Best Paper Award) PDF ACM Bibliometrics

2004

  • R. Marculescu, D. Marculescu, L. Pileggi, “Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems,” in Proc. IEEE Intl. Conference on Computer Design (ICCD), San Jose, CA, Oct. 2004. (Invited paper)
  • D. Marculescu, “Application Adaptive Energy Efficient Clustered Architectures,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004. PDF ACM Bibliometrics
  • E. Talpes, D. Marculescu, “Impact of Technology Scaling on Energy Aware Execution Cache-based Microarchitectures,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004. PDF ACM Bibliometrics
  • P. Stanley-Marbell, D. Marculescu, “Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance,” in Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), Paris, France, Feb. 2004.
  • E. Talpes, V.S.P. Rapaka and D. Marculescu, “Mixed-Clock Issue Queue Design for Energy Aware, High-Performance Cores,” in Proc. ACM/IEEE Asian-South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan.2004.

2003

  • P. Stanley-Marbell and D. Marculescu, “Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems,” in Proc. IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2003.
  • D. Marculescu, N.H. Zamora, P. Stanley-Marbell and R. Marculescu, “Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems,” in Proc. IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2003.
  • V.S.P. Rapaka and D. Marculescu, “A Mixed-Clock Issue Queue Design for Globally Asynchronous, Locally Synchronous Process,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, Aug. 2003. PDF ACM Bibliometrics
  • E. Talpes and D. Marculescu, “A Critical Analysis of Application-Adaptive Multiple Clock Processors,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, Aug. 2003. PDF ACM Bibliometrics
  • P. Stanley-Marbell and D. Marculescu, “Programming Crystalline Hardware,” in Workshop on Non-Silicon Computation (NSC), in conjunction with ACM Intl. Symposium on Computer Architecture (ISCA), San Diego, CA., June 2003.
  • P. Stanley-Marbell and D. Marculescu, “Dynamic Fault-Tolerance Management in Failure-Prone Battery-Powered Systems,” in ACM/IEEE Workshop on Logic and Synthesis (IWLS), Laguna Beach, CA, May 2003.
  • M. Lindwer, D. Marculescu, T. Basten, R. Zimmermann, R. Marculescu, S. Jung, and E. Cantatore, “Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts,” in Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), Munich, Germany, March 2003. (Hot topic session)
  • V.S.P. Rapaka and D. Marculescu, “Pre-characterization Free Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications,” in Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), Munich, Germany, March 2003.
  • S.W. Haga, N. Reeves, R. Barua, and D. Marculescu, “Dynamic Functional Unit Assignment for Low Power,” in Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), Munich, Germany, March 2003.

2002

  • A. Iyer and D. Marculescu, “Power Efficiency of Multiple Clock, Multiple Voltage Cores,” in Proc. IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2002. PDF ACM Bibliometrics
  • N. H. Zamora, P. Stanley-Marbell, R. Marculescu and D. Marculescu, “Pre-Copying: An Improved Code Migration Technique for Future Fault-Tolerant Electronic Textiles,” in First Workshop on Modeling, Analysis and Middleware Support for Electronic Textiles (MAMSET), in conjunction with ASPLOS, San Jose, CA, October 2002.
  • D. Marculescu, R. Marculescu and Pradeep K. Khosla, “Challenges and Opportunities in Electronic Textile Modeling, Analysis and Optimization”, International Interactive Textile for the Warrior Conference, Cambridge, MA, July 2002. (Invited poster)
  • D. Marculescu, R. Marculescu and Pradeep K. Khosla, “Challenges and Opportunities in Electronic Textile Modeling and Optimization”, in Proc. ACM/IEEE Design Automation Conference (DAC), New Orleans, LA, June 2002. (Special session on e-textiles) PDF ACM Bibliometrics
  • A. Iyer and D. Marculescu, “Power-Performance Evaluation of Globally Asynchronous, Locally Synchronous Processors”, in Proc. Intl. Symposium on Computer Architecture (ISCA), Anchorage, AK, May 2002. PDF ACM Bibliometrics
  • R. Marculescu and D. Marculescu, “Does Q=MC2 ?,” in Proc. ACM Intl. Symposium on Quality in Electronic Design (ISQED), San Jose, March 2002. (Invited Paper)

2001

  • D. Marculescu and A. Iyer, “Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis,” in Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2001.
  • E. Talpes and D. Marculescu, “Power Reduction Through Work Reuse”, in Proc. ACM Intl. Symposium on Low Power Electronics and Design (ISLPED), Huntington Beach, Aug. 2001. PDF ACM Bibliometrics
  • A. Iyer and D. Marculescu, “Power Aware Microarchitecture Resource Scaling”, in Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), Munich, Germany, March 2001.

2000

  • A. Iyer and D. Marculescu, “Run-time Scaling of Microarchitecture Resources in a Processor for Energy Savings”, in Proc. KoolChips Workshop, in conjunction with International Symposium on Microarchitecture (MICRO), Monterey, Dec. 2000.
  • D. Marculescu, “Power Efficient Processors Using Multiple Supply Voltages”, in Proc. Workshop on Compilers and Operating Systems for Low Power, in conjunction with International Conference on Parallel Architectures and Compilation Techniques (PACT), Philadelphia, Oct. 2000.
  • D. Marculescu, “Profile-Driven Code Execution for Low Power Dissipation”, in Proc. ACM Intl. Symp. on Low Power Design (ISLPED), Rapallo/Portofino Coast, Italy, July 2000. PDF ACM Bibliometrics
  • D. Marculescu, “On the Use of Microarchitecture-Driven Dynamic Voltage Scaling”, in Proc. Workshop on Complexity-Effective Design, in conjunction with Intl. Symp. on Computer Architecture (ISCA), Vancouver, BC, June 2000.
publications.txt · Last modified: 2014/08/25 23:14 by dianam