Digital Systems Testing and Testable Design

18765 - Fall 2017

Friday, 01:30PM-02:20PM
Hamerschlag Hall 1107

Course Description

We will examine in depth the theory and practice of fault analysis, test generation, and design for testability for digital circuits. Topics to be covered include: defect types and their sources; fault models that include the single stuck-line (SSL), bridging, and delay fault models; fault simulation methods; automatic test pattern generation (ATPG) algorithms for combinational and sequential circuits, including the D-algorithm, PODEM, FAN, and genetic-based algorithms; testability measures; design-for-testability; scan design; test compaction methods; logic-level diagnosis; built-in self-testing (BIST); memory testing; microprocessor testing (i.e,. testing of the Pentium Pro®); and IDDQ current testing. If time permits, we will also consider other topics such as mixed-signal/analog test, micro-electromechanical systems (MEMS) test, and nano-electronics test. As a motivating factor, we also consider the economics of testing.

Course Details