Basic stuff

• Syllabus, v3 (updated 2-Oct-01 to revise deadlines for Proj1, Paper1, Hw3).
  

Current Deadlines

• Homework 5 is out. Revised due date: Dec 17 Mon 6pm.
• Paper Review 3 is out. Revised due date: Dec 17 Mon 6pm.
• Project 3 is out; still due FRI DEC 14 (for URL and demo).

Assignments

• Homework #1 (v1)
• Homework #2 (v2) "Ling" adder problem changed to a verification problem for an "industrial strength" adder. Also, if you just want the description of McFarland's adder itself, it's here. McFarland's web page is here. An, here is some is useful background on basic carry lookahead adders if you want/need some, from 18-347 in Spring01. Here is the LATEST update to just the last problem--simpler and better explanation.
• Homework #3 (v3). newer version with final bug fixes.
• Project 1 part 1(YDD JAVA BDD package) (v1), and
  Project 1 part 2 (PRIMES) version 2 (with a few new bug fixes)
• Paper Review 1: Richard Rudell , "Dynamic variable ordering for ordered binary decision diagrams ", Proc. IEEE/ACM International Conf on CAD,1993.
• Project2 v1 writeup (lecture of 16 Oct) is here.
  Here is our reference on how to use the CUDD BDD package.
  Here is the CUDD home page at Univ Colorado at Boulder.
  Here is documentation on our Checker for Proj2.
  And, if you want additional details about how to do the solve with real Gaussian Elimination, here's the 2 original papers:
  R. E. Bryant, "Algorithmic Aspects of Symbolic Switch Network Analysis," IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 4 (July, 1987), pp. 618-633. (tcad87a.ps, or tcad87a.pdf).
  R. E. Bryant, "Boolean Analysis of MOS Circuits,'' IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 4 (July, 1987), pp. 634-649. (tcad87b.ps, or tcad87b.pdf)
• Homework 4 is here. Here are the blif and genlib documents you need for the techmapping problem. Look on the class AFS account for the code for TSP, for placement, and for the cmuview tcl graphics package. Here is the expanded discussion of the floorplanning problem, the lecture I did on 1-Nov-01.
• Paper Review 2 is here. V. Tiwari, S. Malik, P. Ashar, "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design," IEEE Transactions on CAD, 1996.
• Project 3v1 is out; its after the intro, which is Lec16.
• Homework 5 is here. Nominal due date: Dec 11.
• Paper Review 3 is here. nominal due date: Dec 13. Paper is Jeremy Dion, Louis Monier, "Contour: A Tile-based Gridless Router," DEC Western Research Lab, Technical Report, March 1995. In addition, here is the original paper on tile planes by John Ousterhout, for reference.
  

Lectures

• Lecture 00 - Introduction
• Lecture 01 - Advanced Boolean Algebra
• Lecture 02 - JAVA Introduction
• Lecture 03- BDDs: Representation
• Lecture 04 - BDDs: Manipulation
• Lecture 05 - Formal Verication for FSM Equivalence
• Lecture 06 - 2-Level Minimization
• Lecture 07: Multilevel Minimization I: Models & Methods
• Lecture 08: Multilevel Minimization II: Cube & Kernel Extraction
• Lecture 09: Multilevel Minimization III: Role of Don't Cares
• Lecture 10: Technology Mapping
• Lecture 11: From Logic to Layout
• Lecture 12: Placement I: Annealing
• Lecture 13: Placement II: Recursive Partitioning
• Lecture 14: Placement III: Direct Methods
• Lecture 15: Routing
• Lecture 16 (also Project3): Floorplanning
• Lecture 17: Static Timing
• Lecture 18: Electrical Timing Models and the Elmore Delay
• Lecture 19: Geometric Data Structures
  

Useful links

• http://java.sun.com/docs/books/tutorial/ The Campione and Walrath book, essentially all the tutorials ON LINE, with examples.
• http://www.javasoft.com The SUN central site for Java. You can see product info, download free Java code, etc.
• http://www.gamelan.com ''The official directory for Java**tm'', a good place to snoop for cool Java code you can steal.
• McFarland's web page at Stanford, useful stuff about CMOS design and circuit complexity.
• The CUDD home page at Univ Colorado at Boulder.
• Randy Bryant's publications page in the CS Dept at CMU, for many useful BDD-related papers.