//---------------------------------------------------------------------------
//
//       ASSERT_QUIESCENT_STATE
//
//---------------------------------------------------------------------------
// NAME
//          ASSERT_QUIESCENT_STATE - A concurrent assertion that will 
//		verify a state machine (variable or expression) is in a 
//		known specified state when queried via activating a 
//              'sample_event' expression or global
//		ASSERT_END_OF_SIMULATION macro reference signal.
//
//---------------------------------------------------------------------------

module assert_quiescent_state (clk, reset_n, state_expr, 
		check_value, sample_event);
// synopsys template
  parameter severity_level = 0;
  parameter width=1;
  parameter options = 0;
  parameter msg="VIOLATION";
  input clk, reset_n, sample_event;
  input [width-1:0] state_expr, check_value;

//synopsys translate_off
`ifdef ASSERT_ON

  parameter assert_name = "ASSERT_QUIESCENT_STATE";

  integer error_count;
  initial error_count = 0;

  `include "ovl_task.h"

  `ifdef ASSERT_INIT_MSG
    initial
      ovl_init_msg; // Call the User Defined Init Message Routine
  `endif

  reg r_sample_event;
  initial r_sample_event=1'b0;

  always @(posedge clk) r_sample_event <= sample_event;

 `ifdef ASSERT_END_OF_SIMULATION
    reg r_EOS;
    initial r_EOS=1'b0;
    always @(posedge clk) r_EOS <= `ASSERT_END_OF_SIMULATION;
  `endif

  always @(posedge clk) begin
    `ifdef ASSERT_GLOBAL_RESET
      if (`ASSERT_GLOBAL_RESET != 1'b0) begin
    `else      
      if (reset_n != 0) begin  // active low reset
    `endif
        `ifdef ASSERT_END_OF_SIMULATION
          if ((r_EOS == 1'b0 && `ASSERT_END_OF_SIMULATION ==1'b1) || 
		(r_sample_event == 1'b0 && sample_event == 1'b1)) && 
		(state_expr  != check_value)) begin
        `else
          if ((r_sample_event == 1'b0 && sample_event == 1'b1) && 
		(state_expr  != check_value)) begin
        `endif
            ovl_error("");
          end
      end
  end
`endif
//synopsys translate_on

endmodule