//---------------------------------------------------------------------------
//
//       ASSERT_ORDER_SEQUENCE
//
//---------------------------------------------------------------------------
// NAME
//          ASSERT_ORDER_SEQUENCE - Verify an abirtrary sequence
//                    of events.  The events are specified
//                    using the concate operator.  For example:
//                    {event_1, event_2, event_3, ....}
//                    where event_n is any valid Verilog expression.
//
//---------------------------------------------------------------------------

module assert_order_sequence (clk, reset_n, test_expr);
// synopsys template
  parameter severity_level = 0;
  parameter width=8;
  parameter options=0;
  parameter msg="VIOLATION";
  input clk;
  input reset_n;
  input [0:width-1] test_expr;

//synopsys translate_off
`ifdef ASSERT_ON

  reg  [0:width-1] start_mask; // parameter 32 bit limit will not work
  reg  [0:width-1] error_mask;  
  reg  [0:width-1] last_error_mask;  
  reg  [0:width-1] last_test_expr;  
  reg  found_event;
  integer indx;

  parameter assert_name = "ASSERT_ORDER_SEQUENCE";

  integer error_count;
  initial error_count = 0;

  `include "ovl_task.h"

  `ifdef ASSERT_INIT_MSG
    initial
      ovl_init_msg; // Call the User Defined Init Message Routine
  `endif

  initial 
    begin
      found_event = 0;
      start_mask = 1 << width-1;
      error_mask = ~(start_mask);
      last_error_mask = {width{1'b1}};
      last_test_expr = {width{1'b0}};
      indx = 0;
    end

  always @(posedge clk) 
    begin
    `ifdef ASSERT_GLOBAL_RESET
      if (`ASSERT_GLOBAL_RESET != 1'b0) begin
    `else      
      if (reset_n != 0) begin  // active low reset
    `endif
        found_event = (last_test_expr[indx] == 1'b0) && 
  			(test_expr[indx] == 1'b1);
        last_test_expr <= test_expr;
        if (found_event === 1'b1) 
          begin
            if (indx == (width-1))
              begin // Completed sequence
                last_error_mask <= error_mask;
                error_mask <= ~(start_mask);
                indx = 0;
              end
            else
              begin
                last_error_mask <= error_mask;
                error_mask <= ~((~(error_mask)) >> 1);
                indx <= indx+1;
              end
          end

        if (((found_event === 1'b1) && (|(test_expr & error_mask))) ||
  	  ((found_event === 1'b0) && (|(test_expr & last_error_mask))))
          begin
            ovl_error("");
            last_error_mask <= error_mask;
            error_mask <= ~((~(error_mask)) >> 1);
            indx <= indx+1;
          end
      end
      else begin
        error_count = 0;
        found_event = 0;
        start_mask = 1 << width-1;
        error_mask = ~(start_mask);
        last_error_mask = {width{1'b1}};
        last_test_expr = {width{1'b0}};
        indx = 0;
      end
    end
`endif
//synopsys translate_on

endmodule