//--------------------------------------------------------------------------- // // ASSERT_NEXT // //--------------------------------------------------------------------------- // NAME // ASSERT_NEXT - Checks that "start_event" is asserted, after "num_cks" // cycles "test_expr" will be asserted, or in logical // terms, where X denotes the next cycle operator, // "start_event => X^n (test_expr)" // //--------------------------------------------------------------------------- module assert_next (clk, reset_n, start_event, test_expr); // synopsys template parameter severity_level = 0; parameter num_cks=1; parameter check_overlapping=1; parameter only_if=0; // if 1, test_expr can only appear if a corresponding // start_event occurs parameter options = 0; parameter msg="VIOLATION"; input clk, reset_n, start_event, test_expr; //synopsys translate_off `ifdef ASSERT_ON initial begin if (num_cks <= 0) begin ovl_error("num_cks parameter<=0"); end end parameter assert_name = "ASSERT_NEXT"; integer error_count; initial error_count = 0; `include "ovl_task.h" `ifdef ASSERT_INIT_MSG initial ovl_init_msg; // Call the User Defined Init Message Routine `endif reg [((num_cks>0)?num_cks-1:0):0] monitor; wire [((num_cks>0)?num_cks-1:0):0] monitor_1 = (monitor << 1); initial monitor = 0; always @(posedge clk) begin `ifdef ASSERT_GLOBAL_RESET if (`ASSERT_GLOBAL_RESET != 1'b0) begin `else if (reset_n != 0) begin // active low reset `endif monitor <= (monitor_1 | start_event); if ((check_overlapping == 0) && (monitor_1 != 0) && start_event) begin ovl_error("illegal overlapping condition detected"); end else if (only_if == 1) begin if (!monitor[num_cks-1] && test_expr) begin ovl_error("test_expr without start_event"); end end else begin if (monitor[num_cks-1] && !test_expr) begin ovl_error("start_event without test_expr"); end end end else begin monitor <= 0; end end // always `endif //synopsys translate_on endmodule