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18-747 Paper Review Format

18-747 In-class Presentation Format

Chip Multiprocessors
Title PDF (1) Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing (abstract)
Read byAug. 31
Title PDF (2) Niagara: A 32-way Multithreaded SPARC Processor (abstract)
Read byAug. 31
Title PDF (3) Montecito: A Dual-Core, Dual-Thread Itanium Processor (abstract)
Read bySep. 7
Title PDF (4) Power4 System Microarchitecture (abstract)
Read bySep. 7
Title PDF (5) Power5 Tops on Bandwidth (abstract)
Read bySep. 12
Title PDF (6) Cell Moves Into the Limelight (abstract)
Read bySep. 12
Transactional Architecture
Title PDF (1) Transactional Memory: Architectural Support for Lock-Free Data Structures (abstract)
Read bySep. 14
Title PDF (2) Transactional Lock-Free Execution of Lock-Based Programs (abstract)
Read bySep. 14
Title PDF (3) Composable Memory Transactions (abstract)
Read bySep. 19
Title PDF (4) Transactional Memory Coherence and Consistency (abstract)
Read bySep. 19
Title PDF (5) Unbounded Transactional Memory (abstract)
Read bySep. 21
Title PDF (6) Virtualizing Transactional Memory (abstract)
Read bySep. 21
Title PDF (7) A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay (abstract)
Read bySep. 26
Title PDF (8) Memory State Compressors for Giga-Scale Checkpoint/Restore (abstract)
Read bySep. 26
Non-thread-level Parallel Machines
Title PDF (1) Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams (abstract)
Read bySep. 28
Title PDF (2) PipeRench: a co/processor for streaming multimedia acceleration (abstract)
Read bySep. 28
Title PDF (3) Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture (abstract)
Read byOct. 3
Title PDF (4) The Vector-Thread Architecture (abstract)
Read byOct. 3
Title PDF (5) Imagine: Media Processing with Streams (abstract)
Read byOct. 5
Title PDF (6) Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor (abstract)
Read byOct. 5
Title PDF (7) WaveScalar (abstract)
Read byOct. 10
Title PDF (8) Decoupled Software Pipelining with the Synchronization Array (abstract)
Read byOct. 10
Title PDF (9) The Energy Efficiency of IRAM Architectures (abstract)
Read byOct. 12
Title PDF (10) Smart Memories: a modular reconfigurable architecture (abstract)
Read byOct. 12
Memory Systems
Title PDF (1) Impulse: Building a Smarter Memory Controller (abstract)
Read byOct. 17
Title PDF (2) An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches (abstract)
Read byOct. 17
Title PDF (3) Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures (abstract)
Read byOct. 19
Title PDF (4) TLC: Transmission Line Caches (abstract)
Read byOct. 19
Title PDF (5) Data Cache Prefetching Using a Global History Buffer (abstract)
Read byOct. 24
Title PDF (6) Temporal Streaming of Shared Memory (abstract)
Read byOct. 24
Title PDF (7) Accurate and Complexity-Effective Spatial Pattern Prediction (abstract)
Read byOct. 26
Title PDF (8) Quantifying Load Stream Behavior (abstract)
Read byOct. 26
Title PDF (9) Microarchitecture Optimizations for Exploiting Memory-Level Parallelism (abstract)
Read byOct. 31
Title PDF (10) Continual flow pipelines (abstract)
Read byOct. 31
Simulation and Evaluation
Title PDF (1) Automatically Characterizing Large Scale Program Behavior (abstract)
Read byNov. 7
Title PDF (2) SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling (abstract)
Read byNov. 7
Title PDF (3) The Design of RPM: An FPGA-based Multiprocessor Emulator (abstract)
Read byNov. 9
Title PDF (4) A First-Order Superscalar Processor Model (abstract)
Read byNov. 9
Reliability-Aware Architectures
Title PDF (1) DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design (abstract)
Read byNov. 14
Title PDF (2) Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures (abstract)
Read byNov. 14
Title PDF (3) A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor (abstract)
Read byNov. 16
Title PDF (4) NonStop Advanced Architecture (abstract)
Read byNov. 16
Title PDF (5) ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors (abstract)
Read byNov. 21
Title PDF (6) SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery (abstract)
Read byNov. 21
Title PDF (7) The Case for Lifetime Reliability-Aware Microprocessors (abstract)
Read byNov. 28
Title PDF (8) TRUSS IEEE Micro special issue (abstract)
Read byNov. 28
Variability-Tolerant Architectures
Title PDF (1) Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation (abstract)
Read byNov. 30
Title PDF (2) Temperature-Aware Microarchitecture (abstract)
Read byNov. 30
Title PDF (3) Rescue: A Microarchitecture for Testability and Defect Tolerance (abstract)
Read byDec. 5
Title PDF (4) Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage (abstract)
Read byDec. 5