|Lectures||Mon. & Wed. 2:30 - 4:20 PM in Porter Hall A18c|
|Email list||ece747-official /at/ ece.cmu.edu|
|Email, URL||babak /at/ cmu.edu, http://www.ece.cmu.edu/~babak/|
|Office Hours||Mondays 1:30-2:30 and Thursdays 2:30-3:30|
|Email, URL||mferdman /at/ ece.cmu.edu, http://www.ece.cmu.edu/~mferdman/|
|Office||Hamerschlag A300, Cube A9|
|Office Hours||Tuesdays 3:30-4:30 and Wednesdays 3:30-4:30|
|Admin. Assistant||Matt Koeske|
|Email||koeske /at/ ece.cmu.edu|
The demand for computer system performance continues to grow to keep pace with
our daily needs and to enable solutions to previously infeasible computing
problems. In the recent decades, computer system designers have met the
performance demand by innovating designs to exploit the abundance of
transistors made available through advances in CMOS fabrication.
Unfortunately, there are fundamental sources of bottleneck in sight that may
impede the way to further improvements in performance and scalability of
computer systems. These include the ever-growing gap between processor and
memory performance, design challenges in emerging nanoscale CMOS systems -
including power/thermal density, reliability, and extreme variability in
transistor performance and behavior - and the diminishing returns in exploiting
near-neighbor instruction-level parallelism. Furthermore, in light of
phenomenal increase in system complexity, computer architecture innovation has
been hampered by the absence of fast and accurate design evaluation tools.
These are excellent new challenges for computer architects and there is great
potential for innovation and impact in the years ahead.
In this course, we will discuss results from publications in
recent computer architecture conferences that tackle the above bottlenecks.
Specifically, we will look at:
- architectures to exploit higher levels of parallelism including
multicore/multithreaded designs, designs with custom cores, and reconfigurable
- transactional processor architectures with efficient checkpointing/recovery
mechanisms with applications to low-overhead parallel execution, and both
hardware and software reliability
- memory systems including designs for large speculative windows to enhance
memory-level parallelism, memory streaming techniques, and in-memory
- power-/thermal-aware microarchitecture
- reliable microarchitecture including techniques that are tolerant to
transistor variability, and both hard and soft error
- fast and accurate techniques for microarchitectural performance
The lectures will be primarily based on student presentations of
the assigned papers followed by discussions. All lectures will have
a paper review due at the beginning of the lecture for that lecture's
assigned papers. Besides presentations and reviews, the course will
include an independent research project. The project will be similar
in approach to the projects in 18-741 and 18-742.
18-741 or instructor's consent.
| Reviews || 35% |
| Presentations || 35% |
| Project || 30% |
There is no tolerance for academic dishonesty. Please refer to
the University Policy on cheating and plagiarism. Discussion and group
studies are encouraged by all submitted material must be the student's
individual work (or in case of the project group work).