We recommend that you use ModelSim (vsim) for the simulation and Synplify Pro for the verification of synthesizability of your code.
Add the following line to the end of your .login file, assuming that you are using a csh compatible shell, like tcsh.
If you are using the bash shell, include the following line in either your .bashrc, or your .bash_profile.
Change directory to where you keep your verilog files. Then type:
vsim work.<top-level-module-name> &
vsim -c work.<top-level-module-name>
You can start up Synplify Pro using the following command:
One can also run a text-only version of Synplify Pro using it's batch mode features.
synplify_pro -batch single_run.tcl
Below is a pointer to some example batch mode programs. The first one is a simple single-run program that I have commented to give you some background on how the files need to be set up. There is also a for loop program that uses some more advanced features that I commonly use.
** Note: The graphical version of Synplify Pro 7.1 is currently only working on Sun based machines. The Linux graphical version of Synplify Pro 7.1 REQUIRES RedHat, and will not work correctly on our Suse8.0 Machines(asl/Gameboard cluster). The batch version of Synplify Pro will work on any Linux or Sun machine.
Click here for Synplicity's download page, or contact me if you would like to run a copy of Synplify pro on your own machine. I have Windows, Linux(x86), and Solaris versions available. At CMU we only have the license for the Pro version of Synplify.
Here is a paper that describes many of the additions to the Verilog language. Some information that might be useful in the paper are the ANSI-style input and output declarations (3.15-3.16), and the new sensitivity list information for combinational logic is also pretty cool (3.10-3.11).
Originally authored by Trevor Carlson, 2003