18-742 Research in Parallel Computer Architecture, Fall 2014

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Note that the reviews are due at 11:59 PM on the due date.

Review required for the following two papers, due on Friday, Oct 31.

• Maurice Herlihy and J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.
  • Tom Knight, "An achitecture for mostly functional languages", LFP 1986.
  • James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.
  • Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.
• J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.

Required videos for module 2.5.* in 18-740:

Related readings:

• Sohi et al., “Multiscalar Processors,” ISCA 1995.
• Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005.
• Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution,” MICRO 2001.

Review required (one out of two) due on Wednesday night

• Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007
  • Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.
  • Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.
• Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.
  • Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.
  • Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution”, MICRO 2001.
  • Herlihy and Moss, “Transactional Memory: Architectural Support for Lock-Free Data Structures”, ISCA 1993.

Background lecture and paper (required reading, no need to review):

• Consistency & Coherence Lecture
• Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)

Required review (one out of two) due on Monday night

• Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.
• Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.
  • Kung et al., "On Optimistic Methods for Concurrency Control", TODS 1981.
  • Ranganathan et al., "Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap Between Memory Consistency Models", SPAA 1997.
  • Gniady et al., "Is SC + ILP = RC?", ISCA 1999.

Recommended book

• A Primer on Memory Consistency and Cache Coherence, Chapters 1, 3, 4, 5

Further reading in a different area (system level consistency)

• Lloyd et al., "Stronger Semantics for Low-Latency Geo-Replicated Storage", NSDI 2013.

Amirali's Literature Survey

• Connor et al., "Highlights of the high-bandwidth memory (HBM) standard", Memory Forum 2014.
• Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.
• Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.

Jiyuan's Paper Discussion: (required 1 out of 3 reviews)

• Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.
  • Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.
  • http://lca.ece.utexas.edu/people/kaseridis/papers/ISCA_2010.pdf
  • Fair and High-Performance Memory Control for Persistent Memory Systems"
  • Adaptive History-Based Memory Schedulers
  • A Reinforcement Learning Approach"
• Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.
  • Qureshi et al., "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design", MICRO 2012.
  • Tuck et al., "Scalable Cache Miss Handling for High Memory Level Parallelism", MICRO 2006.
  • Sim et al., "Resilient die-stacked DRAM caches", ISCA 2013.
• Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.
  • Dally et al., "Moving the needle Computer Architecture Research in Academe and Industry", ISCA keynote 2010.

Hui: (required 1 out of 3 reviews)

• Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.
• Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.
• Voskuilen et al., "High-Performance Fractal Coherence", ASPLOS 2014.

Required review for the Memory Forum paper:

Amirali's literature survey:

Doru's literature survey:

• Bois et al., "Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior", ISCA 2013.
• Joao et al., "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs", ISCA 2013.
  • Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.
  • Evelyn Duesterwald et al., "Characterizing and Predicting Program Behavior and its Variability", PACT 2003.
• Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.
  • Andrew Lukefahr et al., "Composite Cores: Pushing Heterogeneity Into a Core", MICRO 2012.
  • Shruti Padmanabha et al., "Trace based phase prediction for tightly-coupled heterogeneous cores", MICRO 2013.
  • Engin Ipek et al., "Core fusion: accommodating software diversity in chip multiprocessors", ISCA 2007.
  • Chris Fallin et al., "The Heterogeneous Block Architecture", ICCD 2014.
  • Carlos Villavieja et al., "Yoga: A Hybrid Dynamic VLIW/OoO Processor", HPS Tech Report 2014.

Yang's literature survey:

• Chao Li et al., "Enabling distributed generation powered sustainable high-performance data center", HPCA 2013.
• Chao Li et al., "Managing Green Datacenters Powered by Hybrid Renewable Energy Systems", ICAC 2014.
• Sen Li et al., "Data center power control for frequency regulation", PES 2014.

• Chatterjee et al., "Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access", MICRO 2012.
• CloudSuite

Kevin's literature survey:

• Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012.
  • Mrinmoy Ghosh et al., "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs", MICRO 2007.
  • Kang et al., "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling", Memory Forum 2014.
  • Ravi K. Venkatesan et al, "Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM", HPCA 2006.
  • K. Ohyu et al, "Quantitative identification for the physical origin of variable retention time: A vacancy-oxygen complex defect model", IEDM 2006.
  • Heesang Kim et al., "Characterization of the Variable Retention Time in Dynamic Random Access Memory", TED 2011.
• Liu et al., "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013.
• Khan et al., "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study", SIGMETRICS 2014.

Hui's literature survey:

• Singh et al., "Cache Coherence for GPU Architectures", HPCA 2013.
• Power et al., "Heterogeneous System Coherence for Integrated CPU-GPU Systems", MICRO 2013.
• Kelm et al., "Cohesion: A Hybrid Memory Model for Accelerators", ISCA 2010.

Jiyuan's literature survey:

• Kamruzzaman et al., "Inter-core Prefetching for Multicore Processors Using Migrating Helper Threads", ASPLOS 2011.
  • Zhou et al., "Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window", PACT 2005.
  • Sundaramoorthy et al., "Slipstream Processors: Improving both Performance and Fault Tolerance", ASPLOS 2000.
• Kumar et al., "SQRL: Hardware Accelerator for Collecting Software Data Structures", PACT 2014.
• He et al., "Efficient Gather and Scatter Operations on Graphics Processors", SC 2007.
  • Carter et al., "Impulse: Building a Smarter Memory Controller", HPCA 1999.
  • Sudan et al., "Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement", ASPLOS 2010.

Yang: (required 1 out of 3 reviews)

• Mutlu et al., "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.
  • Craeynest et al., "Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE)", ISCA 2012.
  • Fields et al., "Slack: Maximizing Performance Under Technological Constraints", ISCA 2002.
  • Fields et al., "Focusing Processor Policies via Critical-Path Prediction", ISCA 2001.
  • Kim et al., "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture", PACT 2004.
• Xu et al., "Providing Fairness on Shared-Memory Multiprocessors via Process Scheduling ", Sigmetrics 2012.
  • Sherwood et al., "Automatically characterizing large scale program behavior", ASPLOS 2002.
  • Sherwood et al., "Phase Tracking and Prediction", ISCA 2003.
  • Ghose et al., "Improving memory scheduling via processor-side load criticality information", ISCA 2013.
  • Qureshi et al., "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO 2006.
  • Stone et al., "Optimal partitioning of cache memory", IEEE Trans. 1992.
• Ebrahimi et al., "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems", TOCS 2012.

Amirali: (required 1 out of 3 reviews)

• Seshadri et al., "RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data", MICRO 2013.
  • Witchel et al., "Mondrian Memory Protection", ASPLOS 2002.
  • Chilimbi et al., "Cache-Conscious Structure Layout", PLDI 1999.
  • Chilimbi et al., "Cache-conscious structure definition", PLDI 1999.
  • Chilimbi et al., "Dynamic Hot Data Stream Prefetching for General-Purpose Programs", PLDI 2002.
  • Kogge et al., "EXECUBE - A New Architecture for Scalable MPPs", ICPP 1994.
  • Gokhale et al., "Processing in memory: The Terasys massively parallel PIM array." Computer 28.4 1995.
  • The Computational RAM (C-RAM) project.
  • Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.
• Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches", PACT 2012.
  • Chen et al., "Free ECC: An efficient error protection for compressed last-level caches", ICCD 2013.
  • Tian et al., "Last-Level Cache Deduplication", ICS 2014.
  • Sathish et al., "Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads", PACT 2012.
• Pekhimenko et al., "Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework", MICRO 2013.

Doru: (required 2 out of 3 reviews)

• Eyerman et al., "Modeling critical sections in amdahl’s law and its implications for multicore design", ISCA 2010.
  • Hill et al., "Amdahl’s Law in the Multicore Era", HPCA 2008.
• Joao et al., "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012.
  • Suleman et al., "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures", ASPLOS 2009.
  • Cai et al., "Meeting Points: Using Thread Criticality to Adapt Multicore Hardware to Parallel Regions", PACT 2008.
  • Srinath et al., "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers", HPCA 2007.
  • Bhattacharjee et al., "Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors", ISCA 2009.
  • Suleman et al., "Data Marshaling for Multi-core Systems", ISCA 2010.
• Subramanian et al., "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems", HPCA 2013.
  • Khubaib et al., "MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP", ISCA 2012.
  • Ipek et al., "Core Fusion: Accommodating Software Diversity in Chip Multiprocessors", ISCA 2007.
  • Joao et al., "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs", ISCA 2013.
  • Sherwood et al., "Phase Tracking and Prediction", ISCA 2003.
  • Bitirgen et al., "Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach", MICRO 2008.

Papers discussed in class by Kevin (and their related papers):

• Seshadri et al., "The Dirty-Block Index", ISCA 2014.
  • Yoon et al., "Virtualized and Flexible ECC for Main Memory", ASPLOS 2010.
  • Kumar et al., "Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy", MICRO 2012.
  • Cantin et al., "Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking", ISCA 2005.
• Ausavarungnirun et al., "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems", ISCA 2012.
  • Waldspurger et al., "Lottery Scheduling: Flexible Proportional-Share Resource Management", OSDI 1994.
  • Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA 1997.
  • Mutlu et al., "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers", ISCA 2008.
  • Fallin et al., "Parallel Application Memory Scheduling", MICRO 2011.
• Chang et al., "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014.

Required reviews, see three due dates below: