Please submit your paper reviews here.
Please create your account as soon as possible so that we can send you the paper for review. If you have any problem with the website, please let me know. (Send me an email at camellyx@gmail.com)

Note that the reviews are due at 11:59 PM on the due date.

• Christian Jacobi, Timothy J. Slegel, Dan F. Greiner: Transactional Memory Architecture and Implementation for IBM System Z. MICRO 2010.
• Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman: ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory. MICRO 2010.
• Jack B. Dennis, David Misunas: A Preliminary Architecture for a Basic Data Flow Processor. ISCA 1974.
• James E. Smith, G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon: The ZS-1 Central Processor. ASPLOS 1987.
• James E. Smith: Decoupled access/execute computer architectures. ISCA 1982

Review required for the following two paper, due on Monday, Nov 17.

• Justin Meza et al., “Memory Errors at Scale: What the Trends Across a Billion-User Web Services Company Foretell”, under submission. (Sent through email, please do not distribute)
• J. Alex Halderman et al., "Lest We Remember: Cold Boot Attacks on Encryption Keys", USENIX Security Symposium 2008.

Reviews required for both papers, due on Wednesday, Nov 12.

• Sridharan et al., "Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults", SC 2013.
  • Bianca Schroeder, Garth A. Gibson, "Disk Failures in the Real World: What Does an MTTF of 1, 000, 000 Hours Mean to You?", FAST 2007.
  • Bianca Schroeder, Garth A. Gibson, "A large-scale study of failures in high-performance computing systems", DSN 2006.
  • Andy A. Hwang, et al., "Cosmic rays don't strike twice: understanding the nature of DRAM errors and the implications for system design", ASPLOS 2012.
  • Bianca Schroeder et al., "DRAM Errors in the Wild: A Large-Scale Field Study", SIGMETRICS 2009.
• Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", SP 2003.
  • J. Alex Halderman et al., "Lest We Remember: Cold Boot Attacks on Encryption Keys", USENIX Security Symposium 2008.

Reviews required for both papers, due on Tuesday, Nov 11.

• Doe Hyun Yoon, Mattan Erez, "Virtualized and flexible ECC for main memory", ASPLOS 2010.
  • T. J. Dell, “A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory,” IBM Microelectronics Division, 1997.
  • Bianca Schroeder et al., "DRAM Errors in the Wild: A Large-Scale Field Study", SIGMETRICS 2009.
  • Edmund B. Nightingale et al., "Cycles, cells and platters: an empirical analysisof hardware failures on a million consumer PCs", EuroSys 2011.
• Xun Jian, Rakesh Kumar, "Adaptive Reliability Chipkill Correct (ARCC)", HPCA 2013.

Review required for the following two papers, due on Friday, Oct 31.

• Maurice Herlihy and J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.
  • Tom Knight, "An achitecture for mostly functional languages", LFP 1986.
  • Frank Schmuck, Jim Wyllie, "Experience with transactions in QuickSilver", SOSP 1991.
  • James Aspnes, Maurice Herlihy, "Wait-Free Data Structures in the Asynchronous PRAM Model", SPAA 1990.
  • Maurice Herlihy, "Wait-free synchronization", TOPLAS 1991.
  • Maurice Herlihy, J. Eliot B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.
  • Ahmad Zmily and Christos Kozyrakis, "Block-Aware Instruction Set Architecture", TACO 2006.
  • Alexander Klaiber, "The Technology Behind Crusoe™ Processors", 2000.
  • J. Larus and R. Rajwar. Transactional Memory. Synthesis Lectures on Computer Architecture (Ch. 1 & 2).
  • Jared Stark, Mary D. Brown, Yale N. Patt, "On pipelining dynamic instruction scheduling logic", MICRO 2000.
  • Christian Jacobi, et al., "Transactional Memory Architecture and Implementation for IBM System Z", MICRO 2012.
  • Sanjay J. Patel et al., “rePLay: a hardware framework for dynamic optimization,” IEEE TC, June 2001.
• J. Gregory Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.
  • Manoj Franklin, Gurindar S. Sohi, "The expandable split window paradigm for exploiting fine-grain parallelsim", ISCA 1992.
  • Sohi et al., “Multiscalar Processors,” ISCA 1995.
  • Steffan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.
  • Luis Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.
  • Akkary and Driscoll, “A dynamic multithreading processor,” MICRO 1998.

Required videos for module 2.5.* in 18-740:

Related readings:

• Sohi et al., “Multiscalar Processors,” ISCA 1995.
• Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005.
• Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution,” MICRO 2001.

Consistency II – Review required (one out of two) due on Wednesday night

• Wenisch et al., "Mechanisms for Store-wait–free Multiprocessors", ISCA 2007
  • Herlihy et al., "Transactional Memory: Architectural Support for Lock-Free Data Structures", ISCA 1993.
  • Steffan et al., "A Scalable Approach to Thread-Level Speculation", ISCA 2000.
• Ceze et al., "BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.
  • Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors", ISCA 2006.
  • Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution”, MICRO 2001.
  • Herlihy and Moss, “Transactional Memory: Architectural Support for Lock-Free Data Structures”, ISCA 1993.

Background lecture and paper (required reading, no need to review):

• Consistency & Coherence Lecture
• Leslie Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans. Computers 28(9): 690-691 (1979)

Consistency I – Required review (one out of two) due on Monday night

• Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors", ISCA 1990.
• Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models", ICPP 1991.
  • Kung et al., "On Optimistic Methods for Concurrency Control", TODS 1981.
  • Ranganathan et al., "Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap Between Memory Consistency Models", SPAA 1997.
  • Gniady et al., "Is SC + ILP = RC?", ISCA 1999.

Recommended book

• A Primer on Memory Consistency and Cache Coherence, Chapters 1, 3, 4, 5

Further reading in a different area (system level consistency)

• Lloyd et al., "Stronger Semantics for Low-Latency Geo-Replicated Storage", NSDI 2013.

Amirali's Literature Survey

• Connor et al., "Highlights of the high-bandwidth memory (HBM) standard", Memory Forum 2014.
• Teller et al., "Translation-Lookaside Buffer Consistency", Computer 1990.
• Basu et al., "Efficient virtual memroy support in big memory servers", ISCA 2013.

Jiyuan's Paper Discussion: (required 1 out of 3 reviews)

• Shao et al., "A Burst Scheduling Access Reordering Mechanism", HPCA 2007.
  • Lee et al., "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS 2010.
  • http://lca.ece.utexas.edu/people/kaseridis/papers/ISCA_2010.pdf
  • Fair and High-Performance Memory Control for Persistent Memory Systems"
  • Adaptive History-Based Memory Schedulers
  • A Reinforcement Learning Approach"
• Loh et al., "3D-Stacked Memory Architectures for Multi-Core Processors", ISCA 2008.
  • Qureshi et al., "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design", MICRO 2012.
  • Tuck et al., "Scalable Cache Miss Handling for High Memory Level Parallelism", MICRO 2006.
  • Sim et al., "Resilient die-stacked DRAM caches", ISCA 2013.
• Zhang et al., "A New Perspective on Processing-in-memory Architecture Design", MSPC 2013.
  • Dally et al., "Moving the needle Computer Architecture Research in Academe and Industry", ISCA keynote 2010.

Hui: (required 1 out of 3 reviews)

• Beu et al., "Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies", MICRO 2011.
• Hechtman et al., "Quick Release: A Throughput-oriented Approach to Release Consistency on GPUs", HPCA 2014.
• Voskuilen et al., "High-Performance Fractal Coherence", ASPLOS 2014.

Required review for the Memory Forum paper: