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readings [2015/10/28 17:04]
nandita [Review Set 7]
readings [2015/12/02 06:08] (current)
nandita [Review Set 11 (due Tuesday, 9th December, 5 PM)]
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 ==== Review Set 7 ==== ==== Review Set 7 ====
   * Perais et al., [[http://​people.irisa.fr/​Arthur.Perais/​data/​ISCA'​14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]],​ //ISCA 2014.// **[Required]**   * Perais et al., [[http://​people.irisa.fr/​Arthur.Perais/​data/​ISCA'​14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]],​ //ISCA 2014.// **[Required]**
-  * Vijaykumar ​et al., [[https://engineering.purdue.edu/~vijay/papers/2002/srtr.pdf | Transient-Fault Recovery Using Simultaneous Multithreading]], //ISCA 2000.// **[Required]**+  * Reinhardt ​et al., [[http://pages.cs.wisc.edu/~shubu/papers/isca2000-srt.pdf | Transient ​fault detection via simultaneous multithreading]], //ISCA 2000.// **[Required]**
   * Constantinides et al. [[https://​users.ece.cmu.edu/​~omutlu/​pub/​ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]],​ //MICRO 2007.// **[Required]**   * Constantinides et al. [[https://​users.ece.cmu.edu/​~omutlu/​pub/​ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]],​ //MICRO 2007.// **[Required]**
 +
 +===== Recitation 10 =====
 +==== Review Set 8 ====
 +  * Mike O'​Connor,​ [[https://​www.ece.cmu.edu/​~calcm/​doku.php?​id=seminars:​seminar_11_03_15|High-bandwidth,​ Energy-efficient DRAM Architectures for GPU Systems]] , //CALCM Talk// **[Required]**
 +
 +===== Lecture 15 ======
 +
 +==== Optional Readings Mentioned in the Lecture ====
 +  * Mutlu et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //ISCA 2008.//
 +  * Muralidhara et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​memory-channel-partitioning-micro11.pdf|Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning]],​ //MICRO 2011.//
 +  * Ebrahimi et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​parallel-memory-scheduling_micro11.pdf|Parallel Application Memory Scheduling]],​ //MICRO 2011.//
 +  * Wang et al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​architecture-aware-distributed-resource-management_vee15.pdf|A-DRM:​ Architecture-aware Distributed Resource Management of Virtualized Clusters]],//​VEE 2015.//
 +  * Moscibroda et al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks]], //USENIX Security 2007.//
 +  * Mutlu et. al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​stfm_micro07-summary.pdf|Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors]],​ //MICRO 2007.//
 +  * Kim et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​atlas_hpca10.pdf|ATLAS:​ A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers]],//​HPCA 2010.//
 +  * Kim et al.,​ [[http://​users.ece.cmu.edu/​~omutlu/​pub/​tcm_micro10.pdf|Thread Cluster Memory Scheduling]],​ //MICRO 2010.//
 +  * Ebrahimi et. al., [[ https://​users.ece.cmu.edu/​~omutlu/​pub/​fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], ​  //​ ASPLOS 2010//
 +
 +
 +===== Lecture 16 =====
 +==== Optional Readings Mentioned in the Lecture ====
 +  * Moscibroda et al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​bless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks]] , //ISCA 2009//
 +  * Das et al., [[http://​research.microsoft.com/​en-us/​um/​people/​moscitho/​Publications/​MICRO2009.pdf |Application-Aware Prioritization Mechanisms for On-Chip Networks]], //MICRO 2009//
 +
 +
 +=====Lecture 17=====
 +==== Optional Readings Mentioned in the Lecture ====
 +  *  Joao et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]],​ //ASPLOS 2012.//
 +  *  Suleman et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]],​ //ASPLOS 2009//
 +  * Gorchowski et al., [[http://​dl.acm.org/​citation.cfm?​id=1032648.1033367 | Best of Both Latency and Throughput]],​ //ICCD 2004.//
 +  * Meza et al., [[https://​www.ece.cmu.edu/​~safari/​pubs/​timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], // IEEE Comp. Arch. Letters, 2012.//
 +  * Yoon, Meza et al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012.//
 +  * Kim et al.,​ [[http://​users.ece.cmu.edu/​~omutlu/​pub/​tcm_micro10.pdf|Thread Cluster Memory Scheduling]],​ //MICRO 2010.//
 +  * Tendler et al., [[http://​www.cc.gatech.edu/​~bader/​COURSES/​UNM/​ece637-Fall2003/​papers/​TDF02.pdf | POWER4 system microarchitecture]],​ //IBM J R&D, 2002.//
 +  * Kalla et al., [[http://​www.ece.cmu.edu/​~ece447/​s12/​lib/​exe/​fetch.php?​media=wiki:​kalla-2004.pdf|IBM Power5 Chip: A Dual-Core Multithreaded Processor]],​ //IEEE Micro 2004.//
 +  * Konngetira et al., [[http://​www.ece.cmu.edu/​~ece742/​f12/​lib/​exe/​fetch.php?​media=kongetira05_niagara.pdf| Niagara: A 32-Way Multithreaded SPARC Processor]],​ //IEEE Micro 2005//
 +  * Luo et. al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014//
 +  * Donghyuk Lee et. al., [[https://​users.ece.cmu.edu/​~omutlu/​pub/​tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]],​ //HPCA 2013//
 +
 +===== Recitation 11=====
 +==== Review Set 9 ====
 +  - Kubaib et al., [[http://​hps.ece.utexas.edu/​pub/​morphcore_micro2012.pdf| MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP]], //MICRO 2012// ​
 +
 +
 +===== Recitation 12 =====
 +==== Review Set 10 (due Friday 27th November, 5 PM) ====
 +   - Mutlu et al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //MICRO 2008//
 +
 +===== Recitation 13 =====
 +
 +==== Review Set 11 (due Tuesday, 9th December, 5 PM)  ==== 
 +  - Hirata et al., [[http://​www.ece.cmu.edu/​~ece742/​f12/​lib/​exe/​fetch.php?​media=hirata92_smt.pdf |An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads]], //ISCA 1992//.
 +  - Tullsen et al., [[https://​www.cs.princeton.edu/​courses/​archive/​fall15/​cos375/​reading/​smt.pdf|Simultaneous Multithreading:​ Maximizing On-Chip Parallelism]],​ //ISCA 1996//.
 +  - Levin and Redell, [[http://​usenix.org/​legacy/​publications/​library/​proceedings/​dsl97/​good_paper.html | How (and How Not) to Write a Good Systems Paper]], //Operating Systems Review 1983//.
 +
 +==== Optional Readings Mentioned in the Lecture ====
 +  - Peyton-Jones,​ [[http://​research.microsoft.com/​en-us/​um/​people/​simonpj/​papers/​giving-a-talk/​giving-a-talk.htm | How to give a good research talk, How to write a great research paper, How to write a good research proposal]]
 +  - Hamming, [[http://​www.cs.virginia.edu/​~robins/​YouAndYourResearch.html |You and Your Research]], //1986//.
 +  - Bransford, J.D., & Johnson, M.K., [[http://​www.cogsci.umn.edu/​docs/​pdfs/​Bransford1972-JVLVB.pdf| Contextual prerequisites for understanding:​ Some investigations of comprehension and recall]], ​ //Journal of Verbal Learning and Verbal Behavior, 11, 717-726//.
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