====== Readings ======

Post your paper reviews for the papers marked** [Review Required]** on the [[http://safari2.ece.cmu.edu/740-f15/ | paper review site ]]. The expectations for these reviews are described in Recitation 1. You can view reviews by other students only after the deadline.

===== Recitation 1 =====
==== Review Set 1====
  - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory
Systems]], //Invited Article in Supercomputing Frontiers and Innovations
(SUPERFRI), 2015.//** [Review Required]** 
  - Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mutlu_yale75_visions2014_talk.pdf |  Rethinking the Systems We Design]], //Technical talk at A Computer Architecture Workshop:
Visions for the Future (Celebrating Yale@75) (YALE@75),
Austin, TX, September 2014//** [Review Required]** 
  - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for
Parallel Graph Processing]], //ISCA 2015.// ** [Optional]** 
  - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** 

==== Optional Readings Mentioned in Lecture ====
  - Smith, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing-smith.pdf | Task of the Referee]],// IEEE Computer 1990//. 
  - Hill and McKinley, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html|Notes on Constructive and Positive Reviewing]]
  -  Thomas Moscibroda and Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf | Memory Performance Attacks: Denial of Memory Service
in Multi-Core Systems]], //Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY),
pages 257-274, Boston, MA, August 2007.//

===== Recitation 2 =====

==== Review Set 2====
  -  Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]],  //ISCA 2015.// **[Review Required]**
  -  Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]**
  -  Jeffrey D. Ullman, [[http://cacm.acm.org/magazines/2015/9/191183-experiments-as-research-validation/fulltext | Experiments as Research Validation: Have We Gone Too Far?]], CACM 2015. **[Review Required]**
  -  Nandita Vijaykumar et al., [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]],  //ISCA 2015.// **[Review Required]**
  - Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Optional]**
==== Optional Readings Mentioned in Lecture ====
  - Moore, [[http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf | Cramming more components onto integrated circuits]], Electronics Magazine, 1965.
  - Kuhn, [[http://www.amazon.com/gp/aw/d/B007USH7J2/ref=tmm_kin_title_0?ie=UTF8&qid=&sr= | The structure of scientific revolutions]], 1962.
  -  Hill and McKinley,  [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html| Notes on Constructive and Positive Reviewing]]
  -  Levin and Redell, [[writing-papers.pdf | How (and how not) to write a good systems paper]], OSR 1983.
  - Jones, [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|How to Write a Great Research Paper]]
  -  Fong, [[rmeta_fong.pdf|How to Write a CS Research Paper: A Bibliography]]
  - Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015.
  - Nickolls and Dally, [[http://sbel.wisc.edu/Courses/ME964/Literature/onGPUcomputingDally2010.pdf | The GPU Computing Era]] , IEEE Micro 2010.
  - Schulte et al., [[http://dx.doi.org/10.1109/MM.2015.71 | Achieving Exascale Capabilities through Heterogeneous Computing]] , IEEE Micro 2015.
  - Michael Mitzenmacher, [[http://cacm.acm.org/magazines/2015/9/191184-theory-without-experiments/fulltext| Theory Without Experiments: Have We Gone Too Far?]], CACM 2015.
  - Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014.
  - Meza et al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]],  IEEE Comp. Arch. Letters, 2012.
  - Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], ICCD 2012.
  - Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], HPCA 2013
  - Lui et al., [[http://research.microsoft.com/pubs/147610/asplos_2011.pdf | Flikker: Saving DRAM Refresh-power through Critical Data Partitioning]], ASPLOS 2011. 
  -  Lefurgy, et al., [[http://dl.acm.org/citation.cfm?id=957972 | Energy Management for Commercial Servers]], IEEE Computer 2003.
  - Larus, [[http://research.microsoft.com/pubs/70581/tr-2008-69.pdf | Spending Moore's Dividend]]  


===== Recitation 3 =====
==== Review Set 3 ====
  -  Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]],  //DSN 2015.// **[Review Required]**
  - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]**
  - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]**
  - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Optional]**
==== Optional Readings Mentioned in Lecture ====
  * Cai et al., [[ https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// 
  * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010//
  * Suleman et al., [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]], //ASPLOS 2009//
  * Kang et al., [[http://users.ece.cmu.edu/~yoonguk/papers/kang-memoryforum14.pdf | Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling]], //Memory Form 2014//
  * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//
   * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// 
   * Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]],  //ISCA 2015.//
   * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.//
   * Dennis et al.,[[https://courses.cs.washington.edu/courses/cse548/11au/Dennis-Dataflow.pdf | A Preliminary Architecture for a Basic Data Flow Processor]], //ISCA 1974.//

===== Lecture 5 =====
==== Optional Readings Mentioned in Lecture ====

  * T. Yeh and Y. Patt [[http://web.cecs.pdx.edu/~herb/ece587s15/Papers/08_yeh_patt_br_predict_1991.pdf  | Two-Level Adaptive Training Branch Prediction]],  //Intl. Symposium on Microarchitecture, November 1991. MICRO Test of Time Award Winner (after 24 years).//
  * Kessler, R. E., [[http://cseweb.ucsd.edu/classes/sp00/cse241/alpha.pdf | The Alpha 21264 Microprocessor]], //IEEE Micro, March/April 1999, pp. 24-36 //
  * McFarling, S., [[http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-36.pdf | Combining Branch Predictors]], //DEC WRL Technical Report, TN-36, June 1993//
  * Smith and Sohi, [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/ieee-proc.superscalar.pdf | The Microarchitecture of Superscalar Processors]], //Proceedings of the IEEE, 1995.//
  * Evers et al., [[http://www.ece.cmu.edu/~ece740/f10/lib/exe/fetch.php?media=analysisofcorrelationandpredictability.pdf | An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work]], //ISCA 1998//
  * Chang et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=717404 | Branch classification: a new mechanism for improving branch predictor performance]], //MICRO 1994//
  * Sprangle et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=604711 | The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference]], //ISCA 1997.//
  * Seznec, [[http://www.irisa.fr/caps/oldcaps/people/seznec/Optim2bcgskew.pdf | An optimized 2bcgskew branch predictor]], //IRISA Tech Report 1993.//
  * Michaud, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.94.63&rep=rep1&type=pdf | Trading conflict and capacity aliasing in conditional branch predictors]], //ISCA 1997//
  * Lee et al., [[http://www-inst.eecs.berkeley.edu/~cs152/sp05/handouts/p4-lee.pdf | The bi-mode branch predictor]], //MICRO 1997.//
  * Eden and Mudge, [[http://web.eecs.umich.edu/~tnm/papers/yags.pdf | The YAGS branch prediction scheme]], //MICRO 1998.//
  * Seznec et al., [[http://www.cs.utah.edu/~rajeev/cs7810/papers/seznec02.pdf | Design tradeoffs for the Alpha EV8 conditional branch predictor]], //ISCA 2002.//
  * Chappell et al., [[http://www.ece.cmu.edu/~ece740/f13/lib/exe/fetch.php?media=chappell_ssmt99.pdf | Simultaneous Subordinate Microthreading (SSMT)]], //ISCA 1999.//
  * Seznec, [[https://classes.soe.ucsc.edu/cmpe221/Spring06/papers/03trace.pdf | Analysis of the O-Geometric History Length branch predictor]], //ISCA 2005//
  * Gochman et al., [[http://www.weblearn.hs-bremen.de/risse/RST/WS04/Centrino/vol7iss2_art03.pdf | The Intel Pentium M Processor: Microarchitecture and Performance]], //Intel Technology Journal, May 2003//
  * Jimenez and Lin, [[https://www.cs.utexas.edu/~lin/papers/hpca01.pdf | Dynamic Branch Prediction with Perceptrons]], //HPCA 2001//
  * Rosenblatt, [[http://catalog.hathitrust.org/Record/000203591 | Principles of Neurodynamics: Perceptrons and the Theory of Brain Mechanisms]], //1962//
  * Seznec and Michaud,  [[http://www.jilp.org/vol8/v8paper1.pdf | A case for (partially) tagged Geometric History Length Branch Prediction]], //JILP 2006.//
  * Andre Seznec, [[http://www.jilp.org/cbp2014/paper/AndreSeznec.pdf | TAGE-SC-L branch predictors]], //CBP 2014//
  * Chappell et al., [[http://hps.ece.utexas.edu/pub/ssmt_isca_29.pdf | Difficult-Path Branch Prediction Using Subordinate Microthreads]], //ISCA 2002.//
  * Jacobsen et al., [[http://people.engr.ncsu.edu/ericro/publications/conference_MICRO-29_jrs.pdf | Assigning Confidence to Conditional Branch Predictions]], //MICRO 1996.//
  * Manne et al., [[http://www.cs.utah.edu/~rajeev/cs7810/papers/manne98.pdf | Pipeline Gating: Speculation Control for Energy Reduction]], //ISCA 1998//
  * Pettis and Hansen, [[http://perso.ensta-paristech.fr/~bmonsuez/Cours/B6-4/Articles/papers15.pdf | Profile Guided Code Positioning]], //PLDI 1990.//
  * Hwu et al., [[http://impact.crhc.illinois.edu/shared/papers/hwu_jsuper93.pdf | The Superblock: An effective technique for VLIW and superscalar compilation,” Journal of Supercomputing]], //1993.//
  * Rotenberg et al., [[http://people.engr.ncsu.edu/ericro/publications/conference_MICRO-29_rbs.pdf | Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching]], //MICRO 1996.//
  * Patel et al., [[https://www.eecs.umich.edu/techreports/cse/97/CSE-TR-335-97.pdf | Critical Issues Regarding the Trace Cache Fetch Mechanism]], //Umich TR, 1997.//
  * A. Peleg, U. Weiser, [[http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5381533.PN.&OS=PN/5381533&RS=PN/5381533 | Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line]], //United States Patent No. 5,381,533, Jan 10, 1995.// 



===== Recitation 4 =====

==== Review Set 4 ====
  * Eiman Ebrahimi et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]],   //ASPLOS 2010// **[Review Required]**
  * Rachata Ausavarungnirun et. al., [[http://users.ece.cmu.edu/~omutlu/pub/MeDiC-for-GPGPUs_pact15.pdf | Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance]],  //PACT 2015// **[Review Required]**
  * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]**
  * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Optional]** 

==== Optional Readings Mentioned in the Lecture ====
  * Kevin Chang et. al., [[ http://www.pdl.cmu.edu/ftp/associated/sbacpad2012_hat.pdf | HAT: Heterogeneous Adaptive Throttling for On-Chip Networks]], //SBAC-PAD 2012//
  * Wilson W. L. Fung et. al., [[ https://www.ece.ubc.ca/~aamodt/papers/wwlfung.micro2007.pdf | Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow]], //MICRO 2007// 
  * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]],  //HPCA 2015//
  * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015//
  * Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for
Parallel Graph Processing]], //ISCA 2015.//  
  * Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//
  * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// 
  * Junwhan Ahn et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], //ISCA 2015.//
  * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.//
  * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.//
  * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014//
  * Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014.
  * Cai et. al. [[http://www.istc-cc.cmu.edu/publications/papers/2013/flash-programming-interference_iccd13.pdf | Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation]]. //ICCD 2013//
  * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], //Intel Technology Journal 2013//
  * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/neighbor-assisted-error-correction-in-flash_sigmetrics14.pdf | Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories]], //SIGMETRICS 2014//
  * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015//
  * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015//
  * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009//
  * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012//
  * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012//

==== Papers Mentioned in the Lecture (Not in Slides) ====
  * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010//
  * Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// 
  * Raoux et. al., [[ http://researcher.watson.ibm.com/researcher/files/us-gwburr/PCM_IBMJRD.pdf | Phase-change random access memory: A scalable technology]], //IBM JRD 2008//
  * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009//

===== Lecture 5 =====
==== Optional Readings Mentioned in the Lecture ====
  * Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory
Systems]], //Invited Article in Supercomputing Frontiers and Innovations
(SUPERFRI), 2015.//
  * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010//
  * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.//
  * Yoongu Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], //ISCA 2014.//
  * Seaborn et.al., [[https://www.blackhat.com/docs/us-15/materials/us-15-Seaborn-Exploiting-The-DRAM-Rowhammer-Bug-To-Gain-Kernel-Privileges.pdf | Exploiting the DRAM rowhammer bug to gain kernel privileges]], //2015//
  * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013//
  * Liu et al., [[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf | RAIDR: Retention-Aware Intelligent DRAM Refresh]],// ISCA 2012.//
  * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.//
  * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.//
  * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015//
  * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015//
  * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012//
  * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012//
  * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014//
  * Subramanian et al., [[The Application Slowdown Model]],  //MICRO 2015.//
  * Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], //HPCA 2013//
  * Wilkes, [[https://www.cs.princeton.edu/courses/archive/fall10/cos375/WilkesCacheElectronics.pdf | Slave Memories and Dynamic Storage Allocation,]] //IEEE Trans. On Electronic Computers, 1965.//
  * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009//
  * Yoongu Kim et al., [[https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf| A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM]], //ISCA 2012//
  * Rau, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.7149&rep=rep1&type=pdf | Pseudo-randomly Interleaved Memory]],// ISCA 1991//
  * Lee et al.,  [[https://users.ece.cmu.edu/~omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf | DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems]], //HPS Technical Report, April 2010.//
  * Ipek et al., [[http://m3.csl.cornell.edu/papers/isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach]], //ISCA 2008//
  * J. Zhao et al., [[https://users.ece.cmu.edu/~omutlu/pub/firm-persistent-memory-scheduling_micro14.pdf | FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems]], //MICRO 2014.//
  * M. Qureshi et al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable high performance main memory system using phase-change memory technology]], //ISCA 2009.// 


===== Recitation 5 =====
==== Review Set 5 ====
  * Justin Meza et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Review Required]** 
  * Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], //Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May 2013.// **[Review Required]**
  * Edmund B. Nightingale et al, [[http://eurosys2011.cs.uni-salzburg.at/pdf/eurosys2011-nightingale.pdf  | Cycles, cells and platters: an empirical analysis of hardware failures on a million consumer PCs]], //Eurosys 2011.// **[Review Required]**
  * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Optional]**
  * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.//  **[Optional]**

===== Lecture 9 =====

==== Optional Readings Mentioned in the Lecture ====
  * Ipek et al., [[http://m3.csl.cornell.edu/papers/isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach]], //ISCA 2008//
  * J. Zhao et al., [[https://users.ece.cmu.edu/~omutlu/pub/firm-persistent-memory-scheduling_micro14.pdf | FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems]], //MICRO 2014.//
  * M. Qureshi et al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable high performance main memory system using phase-change memory technology]], //ISCA 2009.// 
  * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.//
  * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015//
  * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012//
  * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012//
  * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009//
  * Kultursay et al., [[https://users.ece.cmu.edu/~omutlu/pub/sttram_ispass13.pdf | Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative]], //ISPASS 2013.//
  * Meza et al.,  [[http://research.ihost.com/weed2013/papers/storage_memory.pdf | A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory]], //WEED 2013.//

===== Recitation 6 =====

==== Review Set 6 ====
  * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// **[Required]**
  * Black et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4041869&tag=1 | Die Stacking (3D) Microarchitecture]], //MICRO 2006.//  **[Required]**
  * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010//  **[Required]**

===== Recitation 9 =====

==== Review Set 7 ====
  * Perais et al., [[http://people.irisa.fr/Arthur.Perais/data/ISCA'14_EOLE.pdf | EOLE: Paving the Way for an Effective Implementation of Value Prediction]], //ISCA 2014.// **[Required]**
  * Reinhardt et al., [[http://pages.cs.wisc.edu/~shubu/papers/isca2000-srt.pdf | Transient fault detection via simultaneous multithreading]], //ISCA 2000.// **[Required]**
  * Constantinides et al. [[https://users.ece.cmu.edu/~omutlu/pub/ace_micro07.pdf | Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation]], //MICRO 2007.// **[Required]**

===== Recitation 10 =====
==== Review Set 8 ====
  * Mike O'Connor, [[https://www.ece.cmu.edu/~calcm/doku.php?id=seminars:seminar_11_03_15|High-bandwidth, Energy-efficient DRAM Architectures for GPU Systems]] , //CALCM Talk// **[Required]**

===== Lecture 15 ======

==== Optional Readings Mentioned in the Lecture ====
  * Mutlu et al., [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //ISCA 2008.//
  * Muralidhara et al., [[http://users.ece.cmu.edu/~omutlu/pub/memory-channel-partitioning-micro11.pdf|Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning]], //MICRO 2011.//
  * Ebrahimi et al., [[http://users.ece.cmu.edu/~omutlu/pub/parallel-memory-scheduling_micro11.pdf|Parallel Application Memory Scheduling]], //MICRO 2011.//
  * Wang et al., [[https://users.ece.cmu.edu/~omutlu/pub/architecture-aware-distributed-resource-management_vee15.pdf|A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters]],//VEE 2015.//
  * Moscibroda et al., [[https://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks]], //USENIX Security 2007.//
  * Mutlu et. al., [[https://users.ece.cmu.edu/~omutlu/pub/stfm_micro07-summary.pdf|Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors]], //MICRO 2007.//
  * Kim et al., [[http://users.ece.cmu.edu/~omutlu/pub/atlas_hpca10.pdf|ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers]],//HPCA 2010.//
  * Kim et al.,[[http://users.ece.cmu.edu/~omutlu/pub/tcm_micro10.pdf|Thread Cluster Memory Scheduling]], //MICRO 2010.//
  * Ebrahimi et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]],   //ASPLOS 2010//


===== Lecture 16 =====
==== Optional Readings Mentioned in the Lecture ====
  * Moscibroda et al., [[https://users.ece.cmu.edu/~omutlu/pub/bless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks]] , //ISCA 2009//
  * Das et al., [[http://research.microsoft.com/en-us/um/people/moscitho/Publications/MICRO2009.pdf |Application-Aware Prioritization Mechanisms for On-Chip Networks]], //MICRO 2009//


=====Lecture 17=====
==== Optional Readings Mentioned in the Lecture ====
  *  Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.//
  *  Suleman et al., [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]], //ASPLOS 2009//
  * Gorchowski et al., [[http://dl.acm.org/citation.cfm?id=1032648.1033367 | Best of Both Latency and Throughput]], //ICCD 2004.//
  * Meza et al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], // IEEE Comp. Arch. Letters, 2012.//
  * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012.//
  * Kim et al.,[[http://users.ece.cmu.edu/~omutlu/pub/tcm_micro10.pdf|Thread Cluster Memory Scheduling]], //MICRO 2010.//
  * Tendler et al., [[http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf | POWER4 system microarchitecture]], //IBM J R&D, 2002.//
  * Kalla et al., [[http://www.ece.cmu.edu/~ece447/s12/lib/exe/fetch.php?media=wiki:kalla-2004.pdf|IBM Power5 Chip: A Dual-Core Multithreaded Processor]], //IEEE Micro 2004.//
  * Konngetira et al., [[http://www.ece.cmu.edu/~ece742/f12/lib/exe/fetch.php?media=kongetira05_niagara.pdf| Niagara: A 32-Way Multithreaded SPARC Processor]], //IEEE Micro 2005//
  * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014//
  * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013//

===== Recitation 11=====
==== Review Set 9 ====
  - Kubaib et al., [[http://hps.ece.utexas.edu/pub/morphcore_micro2012.pdf| MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP]], //MICRO 2012// 


===== Recitation 12 =====
==== Review Set 10 (due Friday 27th November, 5 PM) ====
   - Mutlu et al., [[http://users.ece.cmu.edu/~omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], //MICRO 2008//

===== Recitation 13 =====

==== Review Set 11 (due Tuesday, 9th December, 5 PM)  ==== 
  - Hirata et al., [[http://www.ece.cmu.edu/~ece742/f12/lib/exe/fetch.php?media=hirata92_smt.pdf |An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads]], //ISCA 1992//.
  - Tullsen et al., [[https://www.cs.princeton.edu/courses/archive/fall15/cos375/reading/smt.pdf|Simultaneous Multithreading: Maximizing On-Chip Parallelism]], //ISCA 1996//.
  - Levin and Redell, [[http://usenix.org/legacy/publications/library/proceedings/dsl97/good_paper.html | How (and How Not) to Write a Good Systems Paper]], //Operating Systems Review 1983//.

==== Optional Readings Mentioned in the Lecture ====
  - Peyton-Jones, [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/giving-a-talk.htm | How to give a good research talk, How to write a great research paper, How to write a good research proposal]]
  - Hamming, [[http://www.cs.virginia.edu/~robins/YouAndYourResearch.html |You and Your Research]], //1986//.
  - Bransford, J.D., & Johnson, M.K., [[http://www.cogsci.umn.edu/docs/pdfs/Bransford1972-JVLVB.pdf| Contextual prerequisites for understanding: Some investigations of comprehension and recall]],  //Journal of Verbal Learning and Verbal Behavior, 11, 717-726//.