18-740/15-740 Computer Architecture – Fall 2013

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===== Guest Lecture "Self-Repairing Architectures" Yanjing Li =====
==== Oct 21, 7:30-9:30pm, CIC 4th Floor Panther Hollow ====

**Outline**

Introduction

Self-repair for processor cores
  * Core sparing
  * Microarchitectural block disabling [Shivakumar 03, Schuchman 05]
  * Core cannibalization [Romanescu 08]
  * Architectural core salvaging [Powell 09]
Self-repair for memories
  * Redundancy-based memory built-in self-repair [Aitken 04]
  * Cache line disabling [Chang 07, Sanda 08]
  * Reconfigurable cache architectures [Shirvani 99]
Self-repair for uncore components [Li 13]

**Short bio:**
Yanjing Li is a research scientist at Intel Labs and a visiting scholar at Stanford University. She received her Ph.D. in Electrical Engineering from Stanford University in 2013, and both a M.S. in Mathematical Sciences and a B.S. in Electrical and Computer Engineering from Carnegie Mellon University. Yanjing has authored and presented award-winning papers at IEEE International Test Conference and IEEE VLSI Test Symposium. She has also been awarded an Intel Divisional Recognition Award. Her research interests include robust system design, validation and test, and computer architecture.

**References**

[Aitken 04] Aitken, R., “A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories,” Proc. Intl. Test Conf., pp. 997-1005, 2004.

[Chang 07] Chang, J., et al., “The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 846-852, 2007.

[Li 13] Li, Y., et al., “Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study,” Proc. IEEE Intl. Test Conf., pp. 1-10, 2013.

[Powell 09] Powell, M.D., et al., “Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance,” Proc. Intl. Symp. on Computer Architecture, pp. 93-104, 2009.

[Romanescu 08] Romanescu, B.F., and D.J. Sorin, “Core Cannibalization Architecture: Improving Lifetime Chip Performance for Multicore Processors in the Presence of Hard Faults,” Proc. Intl. Conf. on Parallel Architectures and Compilation Techniques, pp. 43-51, 2008.

[Sanda 08] Sanda, P.N, et al., “Fault-Tolerant Design of the IBM Power6 Microprocessor,” IEEE Micro, vol. 28, no. 2, pp. 30-38, 2008.

[Schuchman 05] Schuchman, E., and T.N. Vijaykumar, “Rescue: A Microarchitecture for Testability and Defect Tolerance,” Proc. Intl. Symp. on Computer Architecture, pp. 160-171, 2005.

[Shirvani 99] Shirvani, P.P., and E.J. McCluskey, “PADded Cache: A New Fault-Tolerance Technique for Cache Memories,” Proc. VLSI Test Symp., pp. 440-445, 1999.

[Shivakumar 03] Shivakumar, P., et al., “Exploiting Microarchitectural Redundancy for Defect Tolerance,” Proc. Intl. Conf. on Computer Design, pp. 481-488, 2003.
18-740/15-740 Computer Architecture – Fall 2013

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