Readings

Post your paper reviews for the papers marked [Review Required] on the paper review site. The expectations for these reviews are described in module 0. You can view reviews by other students only after the deadline.

Mentioned during module:

• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.

Required:

• Smith, "The Task of the Referee," IEEE Computer 1990.

Mentioned during module:

• Hill and McKinley, "Notes on Constructive and Positive Reviewing".
• Levin and Redell, "How (and how not) to write a good systems paper," OSR 1983.
• Jones, "How to Write a Great Research Paper".

Required:

• Hamming, "You and Your Research," Bell Communications Research Colloquium Seminar, 7 March 1986. [Review Required]
• Mutlu, "Memory Scaling: A Systems Architecture Perspective," Technical talk at MemCon 2013 (MEMCON), Santa Clara, CA, August 2013. [Review Required]
• Patt, "Requirements, bottlenecks, and good fortune: agents for microprocessor evolution," Proceedings of the IEEE, vol. 89, no. 11, 2001. [Review Required]

Mentioned during module:

• Amdahl "Validity of the single processor approach to achieving large scale computing capabilities," AFIPS Conference, April 1967.
• G. E. Moore, "Cramming more components onto integrated circuits," Electronics, April 1965.
• Ronen et al., "Coming Challenges in Microarchitecture and Architecture," Proceedings of the IEEE, vol. 89, no. 11, 2001.

Mentioned during module:

• Fong, "How to Write a CS Research Paper: A Bibliography".

Required:

• Hill, Jouppi, Sohi, “Multiprocessors and Multicomputers,” pp. 551-560 in Readings in Computer Architecture.
• Hill, Jouppi, Sohi, “Dataflow and Multithreading,” pp. 309-314 in Readings in Computer Architecture.
• Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,” ASPLOS 2009. [Review Required] due 9/18
• Joao et al., “Bottleneck Identification and Scheduling in Multithreaded Applications,” ASPLOS 2012.
• Amdahl, “Validity of the single processor approach to achieving large scale computing capabilities,” AFIPS 1967. [Review Required] due 9/20

Mentioned during module:

• Mike Flynn, “Very High-Speed Computing Systems,” Proc. of IEEE, 1966.
• Thornton, “CDC 6600: Design of a Computer,” 1970.
• Annavaram et al., “Mitigating Amdahl’s Law Through EPI Throttling,” ISCA 2005.
• Ipek et al., “Core Fusion: Accommodating Software Diversity in Chip Multiprocessors,” ISCA 2007.
• Hill and Marty, “Amdahl’s Law in the Multi-Core Era,” IEEE Computer 2008.
• Eyerman and Eeckhout, “Modeling critical sections in Amdahl's law and its implications for multicore design,” ISCA 2010.
• Suleman et al., “Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs,” ASPLOS 2008.

Mentioned during module:

• Kumar et al., “Carbon: Architectural Support for Fine-Grained Parallelism on Chip Multiprocessors,” ISCA 2007.

Mentioned during module:

• Joao et al., “Bottleneck Identification and Scheduling in Multithreaded Applications,” ASPLOS 2012.
• Moore, "Cramming more components onto integrated circuits," Electronics, 1965.
• Olukotun et al., "The Case for a Single-Chip Multiprocessor," ASPLOS 1996.
• Tullsen et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” ISCA 1995.
• Kessler, "The Alpha 21264 Microprocessor," IEEE Micro 1999.
• Brown, “Reducing Critical Path Execution Time by Breaking Critical Loops,” UT-Austin 2005.
• Palacharla et al., "Complexity-effective superscalar processors," ISCA 1997.

Mentioned during module:

• Grochowski et al., "Best of both Latency and Throughput," ICCD 2004.
• Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," ISCA 2000.
• Barroso et al., "Memory system characterization of commercial workloads," ISCA 1998.
• Ranganathan et al., "Performance of database workloads on shared-memory systems with out-of-order processors," ASPLOS 1998.
• Kongetira et al., “Niagara: A 32-Way Multithreaded SPARC Processor,” IEEE Micro 2005.
• Chaudhry et al., “Rock: A High-Performance Sparc CMT Processor,” IEEE Micro, 2009.
• Chaudhry et al., “Simultaneous Speculative Threading: A Novel Pipeline Architecture Implemented in Sun's ROCK Processor,” ISCA 2009.
• Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.
• Mutlu et al., “Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance,” IEEE Micro Jan/Feb 2006.
• Tendler et al., "POWER4 system microarchitecture," IBM J R&D, 2002.
• Kalla et al., "IBM Power5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro 2004.
• Le et al., "IBM POWER6 Microarchitecture," IBM J R&D, 2007.
• Kalla et al., "Power7: IBM’s Next-Generation Server Processor," IEEE Micro 2010.
• Annavaram et al., “Mitigating Amdahl’s Law Through EPI Throttling,” ISCA 2005.
• Kumar et al., “Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction,” MICRO 2003.

Required:

• Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,” ASPLOS 2009.
• Suleman et al., "Data marshaling for multi-core architectures," ISCA 2010.
• Suleman et al., "Data Marshaling for Multicore Systems," IEEE Micro 2011.
• Joao et al., “Bottleneck Identification and Scheduling in Multithreaded Applications,” ASPLOS 2012.
• Joao et al., “Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs,” ISCA 2013.

Mentioned during module:

• Amdahl "Validity of the single processor approach to achieving large scale computing capabilities," AFIPS Conference, April 1967.
• Olukotun et al., "The Case for a Single-Chip Multiprocessor," ASPLOS 1996.
• Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.
• Mutlu et al., "Techniques for Efficient Processing in Runahead Execution Engines," ISCA 2005.

Mentioned during module:

• Hill, Jouppi, Sohi, “Multiprocessors and Multicomputers,” pp. 551-560 in Readings in Computer Architecture.
• Culler & Singh, Chapter 1
• Li and Hudak, "Memory Coherence in Shared Virtual Memory Systems, " ACM TOCS 1989.
• Hillis and Tucker, "The CM-5 Connection Machine: a scalable supercomputer," CACM 1993.
• Batcher, "Architecture of a massively parallel processor," ISCA 1980.
• Tucker and Robertson, "Architecture and Applications of the Connection Machine," IEEE Computer 1988.
• Seitz, “The Cosmic Cube,” CACM 1985.

Required:

• Lamport, “How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,” IEEE Transactions on Computers, 1979. [Review Required] due 9/20

Mentioned during module:

• Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," ISCA 1990.
• Gharachorloo et al., "Two Techniques to Enhance the Performance of Memory Consistency Models," ICPP 1991.
• Ceze et al., “BulkSC: bulk enforcement of sequential consistency,” ISCA 2007.

Required:

• Culler & Singh, Chapter 5.1
• Culler & Singh, Chapter 5.3
• Patterson & Hennessy, Chapter 5.8
• Papamarcos and Patel, “A low-overhead coherence solution for multiprocessors with private cache memories,” ISCA 1984. [Review Required] due 9/22
• Laudon and Lenoski, "The SGI Origin: a ccNUMA highly scalable server," ISCA 1997.
• Martin et al., "Token coherence: decoupling performance and correctness," ISCA 2003. [Review Required] due 9/22

Mentioned during module:

• Censier and Feautrier, "A new solution to coherence problems in multicache systems," IEEE Transactions on Computers, 1978.
• Goodman, "Using cache memory to reduce processor-memory traffic," ISCA 1983.
• Lenoski et al., "The Stanford DASH Multiprocessor," IEEE Computer, 1992.
• Baer and Wang, "On the inclusion properties for multi-level cache hierarchies," ISCA 1988.
• Bloom, "Space/time trade-offs in hash coding with allowable errors," CACM 1970.
• Seshadri et al., "The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing," PACT 2012.
• Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA 2012.

Required:

• Sohi et al., “Multiscalar Processors,” ISCA 1995. [Review Required] due 9/24
• Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005. [Review Required] due 9/26
• Rajwar and Goodman, “Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution,” MICRO 2001. [Review Required] due 9/28
• Herlihy and Moss, “Transactional Memory: Architectural Support for Lock-Free Data Structures,” ISCA 1993. [Review Required] due 9/30

Mentioned during module:

• Colohan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.
• Akkary and Driscoll, “A dynamic multithreading processor,” MICRO 1998.
• Burton Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978.
• Gopal et al., “Speculative Versioning Cache,” HPCA 1998.
• Steffan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.
• Franklin and Sohi, “ARB: A hardware mechanism for dynamic reordering of memory references,” IEEE TC 1996.
• Moshovos et al., “Dynamic Speculation and Synchronization of Data Dependences,” ISCA 1997.
• Chrysos and Emer, “Memory Dependence Prediction using Store Sets,” ISCA 1998.
• Dubois and Song, “Assisted Execution,” USC Tech Report 1998.
• Chappell et al., “Simultaneous Subordinate Microthreading (SSMT),” ISCA 1999.
• Zilles and Sohi, “Execution-based Prediction Using Speculative Slices”, ISCA 2001.
• Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.
• Sundaramoorthy et al., “Slipstream Processors: Improving both Performance and Fault Tolerance,“ ASPLOS 2000.
• Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005.
• Martinez and Torrellas, "Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications," ASPLOS 2002.
• Rajwar and Goodman, "Transactional Lock-Free Execution of Lock-Based Programs," ASPLOS 2002.
• Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,” ASPLOS 2009.
• Dice et al., "Early experience with a commercial hardware transactional memory implementation," ASPLOS 2009.
• Wang et al., "Evaluation of blue Gene/Q hardware support for transactional memories," PACT 2012.
• Jensen et al., “A New Approach to Exclusive Data Access in Shared Memory Multiprocessors,” LLNL Tech Report 1987.
• Jacobi et al., “Transactional Memory Architecture and Implementation for IBM System Z,” MICRO 2012.
• Chung et al., “ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory,” MICRO 2010.

Mentioned during module:

• Denning, P. J. (1970). Virtual Memory. ACM Computing Surveys, 2(3).
• Jacob, B., & Mudge, T. (1998). Virtual memory in contemporary microprocessors. IEEE Micro.
• Patterson & Hennessy's Computer Organization and Design: The Hardware/Software Interface Chapter 5.4
• Computer Organization by Hamacher, Vranesic, and Zaky, McGraw-Hill. Chapter 8.8

Required:

• Wilkes, M. V. (1965). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers. [Review Required] due 10/1

Mentioned during module:

• Patterson & Hennessy's Computer Organization and Design: The Hardware/Software Interface Chapter 5.1-5.3
• Computer Organization by Hamacher, Vranesic, and Zaky, McGraw-Hill. Chapter 8.1-8.7
• Liptay, J. S. (1968). Structural aspects of the system/360 model 85: II the cache. IBM Syst. J.

Required:

• Belady, L. A. (1966). A study of replacement algorithms for a virtual-storage computer. IBM Syst. J. [Review Required] due 10/1

Mentioned during module:

• Qureshi, M. K., Lynch, D. N., Mutlu, O., & Patt, Y. N. (2006). A Case for MLP-Aware Cache Replacement. Proceedings of the 33rd annual international symposium on Computer Architecture.
• Jouppi, N. P. (1990). Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. Proceedings of the 17th annual international symposium on Computer Architecture.
• Rau, B. R. (1991). Pseudo-randomly interleaved memory. Proceedings of the 18th annual international symposium on Computer architecture.
• Seznec, A. (1993). A case for two-way skewed-associative caches. Proceedings of the 20th annual international symposium on computer architecture.

Required:

• Qureshi et al., “A Case for MLP-Aware Cache Replacement,” ISCA 2005. [Review Required] due 10/3
• Pekhimenko et al., "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches," PACT 2012. [Review Required] due 10/6
• Qureshi and Patt, “Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,” MICRO 2006. [Review Required] due 10/8
• Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address both Cache Pollution and Thrashing,” PACT 2012.

Mentioned during module:

• Pekhimenko et al., “Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency,” MICRO 2013.
• Suh et al., “A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning,” HPCA 2002.
• Kim et al., “Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture,” PACT 2004.
• Lin et al., “Gaining Insights into Multi-Core Cache Partitioning: Bridging the Gap between Simulation and Real Systems,” HPCA 2008.
• Cho and Jin, “Managing Distributed, Shared L2 Caches through OS-Level Page Allocation,” MICRO 2006.
• Qureshi, “Adaptive Spill-Receive for Robust High-Performance Caching in CMPs,” HPCA 2009.
• Hardavellas et al., “Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches,” ISCA 2009.
• Fedorova et al., “Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler,” PACT 2007.

Required:

• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. [Review Required] due 10/10
• Ipek et al., “Self Optimizing Memory Controllers: A Reinforcement Learning Approach,” ISCA 2008. [Review Required] due 10/13

Mentioned during module:

• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA 2012.
• Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.
• Seshadri et al., “RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” CMU CS Tech Report 2013.
• David et al., “Memory Power Management via Dynamic Voltage/Frequency Scaling,” ICAC 2011.
• Cai et al., “Error Analysis and Retention-Aware Error Management for NAND Flash Memory,” ITJ 2013.
• Das et al., “Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems,” HPCA 2013.
• Ebrahimi et al., “Fairness via Source Throttling,” ASPLOS 2010, ACM TOCS 2012.
• Lee et al., “Prefetch-Aware DRAM Controllers,” MICRO 2008, IEEE TC 2011.

Required:

• Qureshi et al., “Scalable high performance main memory system using phase-change memory technology,” ISCA 2009. [Review Required] due 10/15

Mentioned during module:

• Meza et al., “A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory,” WEED 2013.
• Kultursay et al., “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” ISPASS 2013.
• Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA 2009, CACM 2010, Top Picks 2010.
• Meza et al., “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters 2012.
• Yoon et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012 Best Paper Award.

Required:

• Mutlu and Moscibroda, “Parallelism-Aware Batch Scheduling,” ISCA 2008. [Review Required] due 10/20
• Subramanian et al., “MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,” HPCA 2013. [Review Required] due 10/26
• Ebrahimi et al., “Fairness via Source Throttling,” ASPLOS 2010, ACM TOCS 2012. [Review Required] due 10/30

Mentioned during module:

• Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO 2011.
• Moscibroda and Mutlu, “Memory Performance Attacks,” USENIX Security 2007.
• Mutlu and Moscibroda, “Stall-Time Fair Memory Access Scheduling,” MICRO 2007.
• Kim et al., “ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,” HPCA 2010.
• Kim et al., “Thread Cluster Memory Scheduling,” MICRO 2010, IEEE Micro 2011.
• Muralidhara et al., “Memory Channel Partitioning,” MICRO 2011.
• Ausavarungnirun et al., “Staged Memory Scheduling,” ISCA 2012.
• Ebrahimi et al., “Prefetch-Aware Shared Resource Management for Multi-Core Systems,” ISCA 2011.

Required:

• Moscibroda and Mutlu, “A Case for Bufferless Routing in On-Chip Networks,” ISCA 2009. [Review Required] due 11/1
• Fallin et al., “CHIPPER: A Low-Complexity Bufferless Deflection Router,” HPCA 2011. [Review Required] due 11/1
• Fallin et al., “MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect,” NOCS 2012.
• Das et al., “Application-Aware Prioritization Mechanisms for On-Chip Networks,” MICRO 2009.
• Das et al., “Aergia: Exploiting Packet Latency Slack in On-Chip Networks,” ISCA 2010, IEEE Micro 2011. [Review Required] due 10/28
• Kevin Chang et al., "HAT: Heterogeneous Adaptive Throttling for On-Chip Networks," SBAC-PAD 2012
• Dally, “Route Packets, Not Wires: On-Chip Interconnection Networks,” DAC 2001.

Recommended:

• Wentzlaff et al., “On-Chip Interconnection Architecture of the Tile Processor,” IEEE Micro 2007.
• Mullins et al., “Low-Latency Virtual-Channel Routers for On-Chip Networks,” ISCA 2004.
• Tobias Bjerregaard, Shankar Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys (CSUR) 2006.

Mentioned during module:

• Grot et al. “Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip,” MICRO 2009.
• Grot et al., “Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees,” ISCA 2011, IEEE Micro 2012.
• Janak H. Patel, "Processor-Memory Interconnections for Multiprocessors," ISCA 1979
• Gottlieb et al., "The NYU Ultracomputer-designing MIMD, shared-memory parallel machine," ISCA 1982
• Chris Fallin et al., "HiRD: A Low-COmplexity, Energy-Efficient Hierarchical Ring Interconnect" SAFARI Technical Report
• Thinking Machines Corp., "The Connection Machine CM-5 Technical Summary," Jan. 1992
• Seitz, "The Cosmic Cube," CACM 1985
• Glass and Ni, "The Turn Model for Adaptive Routing," ISCA 1992
• George Nychis et al., "On-Chip Network from a Networking Perspective: Congestion and Scalability in Many-core Interconnects," SIGCOMM 2012
• George Nychis et al., "Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need?," HOTNETS 2010
• Galles, “Spider: A High-Speed Network Interconnect,” IEEE Micro 1997
• Dally, “Virtual Channel Flow Control,” ISCA 1990
• M. Karo, et al., "Input Versus Output Queuing on a Space-Division Packet Switch," IEEE Transactions on Communications 1987

Review Required:

• Lindholm, E., Nickolls, J., Oberman, S., & Montrym, J. (2008). NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE.[Review Required]: due 11/4
• Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt: Improving GPU performance via large warps and two-level warp scheduling. MICRO 2011: 308-317 [Review Required]: due 11/4

Mentioned during module:

• p50-fatahalian.pdf|Fatahalian, K., & Houston, M. (2008). A closer look at GPUs. Commun. ACM.
• Flynn, M. J. (1966). Very high-speed computing systems. Proceedings of the IEEE.
• Russell, “The CRAY-1 computer system,” CACM 1978.
• Peleg and Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro, 1996.
• Fung, W. W. L., Sham, I., Yuan, G., & Aamodt, T. M. (2007). Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture.
• Gurd, J. R., Kirkham, C. C., & Watson, I. (1985). The Manchester prototype dataflow computer. Commun. ACM.

Required:

• Dennis and Misunas, “A preliminary architecture for a basic data flow processor,” ISCA 1974.[Review Required]: 11/8
• Keckler et al., GPUs and the Future of Parallel Computing, IEEE Micro 2011. [Review Required]: 11/8
• Arvind and Nikhil, "Executing a program on the MIT tagged-token dataflow architecture," IEEE TC 1990.
• Patt et al., "HPS, a new microarchitecture: rationale and introduction," MICRO 1985.
• Patt et al., "Critical issues regarding HPS, a high performance microarchitecture," MICRO 1985.

Mentioned during module:

• Gurd et al., "The Manchester prototype dataflow computer," CACM 1985.
• Lee and Hurson, "Dataflow Architectures and Multithreading," IEEE Computer 1994.
• Sankaralingam et al., “Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture,” ISCA 2003.
• Burger et al., “Scaling to the End of Silicon with EDGE Architectures,” IEEE Computer 2004.
• Dennis and Misunas, "A preliminary architecture for a basic data flow processor," ISCA 1974.
• Treleaven et al., “Data-Driven and Demand-Driven Computer Architecture,” ACM Computing Surveys 1982.
• Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986.
• Hwu and Patt, “HPSm, a high performance restricted data flow architecture having minimal functionality,” ISCA 1986.

Required:

• Kung, H. T. (1982). Why Systolic Architectures? IEEE Computer. [due 11/11]

Mentioned during module:

• Fisher, J. A. (1983). Very Long Instruction Word architectures and the ELI-512. Proceedings of the 10th annual international symposium on Computer architecture.
• Smith, J. E. (1982). Decoupled access/execute computer architectures. Proceedings of the 9th annual symposium on Computer Architecture.
• Smith, J. E. (1984). Decoupled access/execute computer architectures. ACM Trans. Comput. Syst.
• Smith, J. E., Dermer, G. E., Vanderwarn, B. D., Klinger, S. D., & Rozewski, C. M. (1987). The ZS-1 central processor. Proceedings of the second international conference on Architectual support for programming languages and operating systems.
• Smith, J. E. (1989). Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. S. (1986). Warp architecture and implementation. Proceedings of the 13th annual international symposium on Computer architecture.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. (1987). The warp computer: Architecture, implementation, and performance. IEEE Transactions on Computers.
• Rau and Fisher, “Instruction-level parallel processing: history, overview, and perspective,” Journal of Supercomputing, 1993.
• Faraboschi et al., “Instruction Scheduling for Instruction Level Parallel Processors,” Proc. IEEE, Nov. 2001.

Review Required:

• Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978. [due 11/13]
• Tullsen et al., “Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor,” ISCA 1996. [due 11/13]

Recommended:

• Burton J. Smith, "Architecture and applications of the HEP multiprocessor computer system

Mentioned during module:

• Spracklen and Abraham, “Chip Multithreading: Opportunities and Challenges,” HPCA Industrial Session 2005.
• Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004.
• Eyerman and Eeckhout, “A Memory-Level Parallelism Aware Fetch Policy for SMT Processors,” HPCA 2007.
• Hirata et al., “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads,” ISCA 1992.
• Gabor et al., “Fairness and Throughput in Switch on Event Multithreading,” MICRO 2006.
• Agarwal et al., “APRIL: A Processor Architecture for Multiprocessing,” ISCA 1990.
• Kim et al., “Thread Cluster Memory Scheduling,” MICRO 2010
• Kim et al., “Thread Cluster Memory Scheduling,” IEEE Micro 2011.
• Ausavarungnirun et al., “Staged memory scheduling: achieving high performance and scalability in heterogeneous systems,” ISCA 2012.
• Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO 2011.
• Meza et al., “Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management,” IEEE CAL 2012.
• Yoon et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012.
• Thornton, "Design of a Computer: The Control Data 6600," 1970.
• Thornton, "Parallel Operation in the Control Data 6600," AFIPS 1964.
• McNairy and Bhatia, “Montecito: A Dual-Core, Dual-Thread Itanium Processor,” IEEE Micro 2005.

Mentioned during module:

• Yamamoto et al., “Performance Estimation of Multistreamed, Supersealar Processors,” HICSS 1994.
• Tullsen et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” ISCA 1995.
• Snavely and Tullsen, "Symbiotic Jobscheduling for a Simultaneous Multithreading Processor," ASPLOS 2000.
• Jacobsen et al., "Assigning confidence to conditional branch predictions," MICRO 1996.
• Brown and Tullsen, “Handling Long-latency Loads in a Simultaneous Multithreading Processor,” MICRO 2001.
• El-Moursy and Albonesi, “Front-End Policies for Improved Issue Efficiency in SMT Processors,” HPCA 2003.
• Raasch and Reinhardt, “The Impact of Resource Partitioning on SMT Processors,” PACT 2003.
• Eyerman and Eeckhout, “A Memory-Level Parallelism Aware Fetch Policy for SMT Processors,” HPCA 2007.
• Ramirez et al., “Runahead Threads to Improve SMT Performance,” HPCA 2008.
• Van Craeynest et al., "MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor," HiPEAC 2009.
• Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004.
• Lebeck et al., "A Large, Fast Instruction Window for Tolerating Cache Misses," ISCA 2002.
• Marr et al., “Hyper-Threading Technology Architecture and Microarchitecture,” Intel technology Journal 2002.

Review Required:

• Chappell et al., “Simultaneous Subordinate Microthreading (SSMT),” ISCA 1999. [due 11/15]
• Snavely and Tullsen, “Symbiotic Jobscheduling for a Simultaneous Multithreading Processor,” ASPLOS 2000. [due 11/15]

Mentioned during module:

• Reinhardt and Mukherjee, “Transient Fault Detection via Simultaneous Multithreading,” ISCA 2000.
• Rotenberg, "AR-SMT: a microarchitectural approach to fault tolerance in microprocessors," Fault-Tolerant Computing 1999.
• Mukherjee et al., “Detailed Design and Evaluation of Redundant Multithreading Alternatives,” ISCA 2002.
• Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 1999.
• Austin, “DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,” MICRO 1999.
• Qureshi et al., “Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors,” DSN 2005.
• Zilles et al., “The use of multithreading for exception handling,” MICRO 1999.
• Dubois and Song, “Assisted Execution,” USC Tech Report 1998.
• Chappell et al., "Difficult-path branch prediction using subordinate microthreads," ISCA 2002.
• Zilles and Sohi, “Execution-based Prediction Using Speculative Slices”, ISCA 2001.

Mentioned during module:

• Colohan et al., “A Scalable Approach to Thread-Level Speculation,” ISCA 2000.
• Sundaramoorthy et al., “Slipstream Processors: Improving both Performance and Fault Tolerance,“ ASPLOS 2000.
• Zhou, “Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window,” PACT 2005.

Review Required:

• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE. [due 11/18]

Mentioned during module:

• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Hwu, W. W., & Patt, Y. N. (1987). Checkpoint repair for out-of-order execution machines. Proceedings of the 14th annual international symposium on Computer architecture.
• Patt, Y. N., Hwu, W. M., & Shebanow, M. (1985). HPS, a new microarchitecture: rationale and introduction. Proceedings of the 18th annual workshop on Microprogramming.
• Tomasulo, R. M. (1967). An Efficient Algorithm for Exploiting Multiple Arithmetic Units. IBM Journal of Research and Development.
• Patt, Y. N., Melvin, S. W., Hwu, W. M., & Shebanow, M. C. (1985). Critical issues regarding HPS, a high performance microarchitecture. Proceedings of the 18th annual workshop on Microprogramming.
• Sazeides, Y., & Smith, J. E. (1997). The predictability of data values. Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture.

Review Required:

• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro. [due 11/20]
• Palacharla et al., Complexity-Effective Superscalar Processors, ISCA 1997 [due 11/27]

Mentioned during module:

• Moshovos et al., “Dynamic Speculation and Synchronization of Data Dependences,” ISCA 1997.
• Chrysos and Emer, “Memory Dependence Prediction using Store Sets,” ISCA 1998.
• Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., & Roussel, P. (2001). The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal.
• Yeager, K. C. (1996). The MIPS R10000 Superscalar Microprocessor. IEEE Micro.
• Tendler et al., "POWER4 system microarchitecture," IBM J R&D, 2002.
• Gurd, J. R., Kirkham, C. C., & Watson, I. (1985). The Manchester prototype dataflow computer. Commun. ACM.

Review Required:

• Hwu et al., "The Superblock: An Effective Technique for VLIW and superscalar compilation," J of SC 1991. [due 11/22]

Mentioned during module:

• Kung, H. T. (1982). Why Systolic Architectures? IEEE Computer.
• Smith, J. E. (1982). Decoupled access/execute computer architectures. Proceedings of the 9th annual symposium on Computer Architecture.
• Smith, J. E. (1984). Decoupled access/execute computer architectures. ACM Trans. Comput. Syst.
• Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE TC 1981.
• Mahlke et al., "Effective Compiler Support for Predicated Execution Using the Hyperblock," MICRO 1992.
• Melvin and Patt, "Enhancing Instruction Scheduling with a Block-Structured ISA," IJPP 1995.
• Hao et al., "Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures," MICRO 1996.
• Huck et al., "Introducing the IA-64 Architecture," IEEE Micro 2000.

Review Required:

• S. Mcfarling, "Combining branch predictors," WRL Technical Note TN-36 (1993). [due 12/2]

Mentioned during module:

• Ball and Larus, "Branch Prediction for Free," PLDI 1993.
• Smith, J. E. (1981). A study of branch prediction strategies. Proceedings of the 8th annual symposium on Computer Architecture.
• Yeh, T.-Y., & Patt, Y. N. (1991). Two-level adaptive training branch prediction. Proceedings of the 24th annual international symposium on Microarchitecture.
• Kessler, "The Alpha 21264 Microprocessor," IEEE Micro 1999.
• Chang, P.-Y., Hao, E., Yeh, T.-Y., & Patt, Y. (1994). Branch classification: a new mechanism for improving branch predictor performance. Proceedings of the 27th annual international symposium on Microarchitecture.
• Kim, H., Mutlu, O., Stark, J., & Patt, Y. N. (2005). Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture.
• Kim et al., "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths," MICRO 2006.
• Riseman and Foster, "The Inhibition of Potential Parallelism by Conditional Jumps," IEEE Transactions on Computers 1972.
• Chang, Hao, and Patt, "Target Prediction for Indirect Jumps," ISCA 1997.

Review Required:

• Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt, "Runahead Execution: An Effective Alternative to Large Instruction Windows," IEEE Micro Top Picks 2003. [due 12/4]
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," IEEE Micro Top Picks 2006. [due 12/4]
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns," MICRO 2005. Optional due 12/6

Mentioned during module:

• Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.
• Armstrong et al., "Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery," MICRO 2004.