# Homework 8: Main Memory

Due MONDAY October 26, 1998

Problem 1:

Draw a picture of a 7-bank interleaved memory similar to the one on slide 7 (handout page 4) of lecture 14 but using address values instead of array index values. Assume that each bank holds 8-byte words (so address 0 is in bank 0, address 8 is in bank 1, address 0x10 in bank 2, etc.) Show the placement of all addresses from 0 to address 0x190 or 0 to address decimal 400. (i.e., the first fifty-one 8-byte words in memory). Indicate the address of each word in each memory bank. You may use either hex or decimal notation (but say which you are using). Using a spreadsheet for this could be a good idea.

Problem 2:

Draw a picture of how a 8-by-8 array of 8-byte values maps into a 7-bank interleaved memory (identical in layout to the array in part 1 above). Use C ordering (as opposed to Fortran ordering) and label each position in the banks with the subscript values rather than the memory address (so you should have a picture similar to the ones used in the class lectures; assume that address 0 contains element [0][0]; you may leave out the "[" and "]" characters if they are inconvenient). Again, a spreadsheet with slight cleverness on the numeric formatting could make this easy.

• Underline all the elements of row 2 (first subscript value 2).
• Boldface all the elements of column 1 (second subscript value 1).
• Italicize all the elements of the main diagonal (first subscript = second subscript).
• Alternately you may color code, highlight, etc. the above three groups of elements as long as you provide a legend.
• Is there a bank conflict accessing the rows, columns, or main diagonal of this example array?

Problem 3:

You are building an embedded product that has an on-CPU-chip I-cache, but no room for D-cache. You decide to use a single 64 Mbit SDRAM chip that provides 4-way interleaving using 4 internal DRAM banks to give you a small amount of caching effect within the SDRAM. Assume that each bank buffers a 2 KB row, and you have arranged the address lines so that consecutive rows sequence through the banks (in other words, this looks like an interleaved memory system accessed in 2 KB chunks per bank). Write the dinero command line to simulate the caching effects available from the 4 SDRAM banks (assume that a valid trace is presented to dinero via a Unix pipe, and has already taken into account the on-CPU-chip I-cache effects). You may want to actually run the command line on a toy trace to verify the syntax, but this question is asking only for the actual dinero command line. Data words accessed by the CPU are 8 bytes in size. You must set the cache size, block size, write policy, write allocation policy, associativity, word size, and bus width in your command line (explicitly specify all values, even if identical to default values). Remember that the "bus" is on the DRAM-side of this "cache", and is not the system bus.