-------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "RAIDR: Retention-Aware Intelligent DRAM Refresh" by Liu et al. Student reviewer: Name withheld to protect the diligent. Paper Summary: The paper discusses RAIDR, a proposed solution to the performance and energy penalties caused by DRAM refresh. RAIDR is an intelligent, low-cost modification to the DRAM memory controller that exploits the fact that only a small fraction of the cells in a DRAM actually need to be refreshed after 64 ms; the remaining majority can be refreshed with less frequency. RAIDR ameliorates this wastage by refreshing cells at different refresh rates based on their retention time. This paper's method of doing this is to categorize cells into bins that cover certain refresh rate intervals. The controller profiles the rows (i.e. determines their retention rates), stores rows into bins using 10 a bloom filter, and performs the refresh of each bin separately at the appropriate refresh rate. The paper also explains the disadvantages of uniform DRAM refresh: memory accesses take longer, there is a loss of parallelism across DRAM banks, and there are many row misses after a refresh. More- over, a lot of energy is consumed, and DRAM does not scale well as a result. Strengths: * In the introduction, the paper provides a clear description of the issues with DRAM refresh. * The solution addresses the problem well, and the approach is laid out methodically. Each section has a breakdown of the section topic and summary at the end for utmost clarity. * The paper describes past solution to the problem, which give context to the solution proposed by the authors. Weaknesses: * 3D-stacked DRAM is not defined as well as the other concepts in the paper. This makes it difficult to understand why RAIDR is applicable to it. * It was not clear why the solution was low-cost. It was mentioned several times but not really explained. Ideas for Improvement: * Briefly explain the concept of 3D-stacked DRAM. This was the only concept that was not really defined clearly even though the paper did a good job with the rest. * Since the solution claims to be low-cost, include some cost analysis of RAIDR. Lessons Learned: I now have a good understanding of why DRAM refresh poses a problem. I gained some insight into some of the particulars of the issue such as DRAM refresh rate variation caused by temperature change. Finally, I learned that if DRAM memories need to become larger in the future, we will need intelligence, scalable solutions such as RAIDR or move to alternate memory technologies. -------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems" by Moscibroda and Mutlu Student reviewer: Name withheld to protect the diligent. 1) Summary This paper attempts to introduce and solve the problem of a memory performance hog: when an application in a multicore system “steals” the shared off chip memory access because of unfairness in the memory system design. It walks the reader through the high details of then- modern DRAM architecture, and the culprit scheduling algorithm, with real experiment data to backup the claim. Then, they define fairness and propose a system, FairMem, where each thread in the system is serviced such that their overall slowdown is roughly the same. 2) Strengths I really liked how detailed the paper was, especially for the background information. It helped to really understand the problem the authors were trying to solve by showing how every detail contributed to the unfairness issue. The proposed solution is a clever workaround, however the implementation of it seems very complex, if it to be done in hardware. 3) Weaknesses I still feel iffy about their claim that the only way to solve the problem is through changing the hardware. I believe there is a way to do it on an OS level where it looks through the code of all programs, decides where there are memory accesses and schedules/reschedules threads based on that. Sure, that might complicate scheduling, but software is easy to change than hardware. 4) Ideas/Suggestions One concern I had with the MPH was that it all stemmed from the assumption that everything was run on the multicore CPU. However, once GPUs were becoming a big thing, wouldn't the OS port applications that utilize a ton of data (such as MPHs) to the GPUs, which run on their own context, while the memory bus opens up for other, low-memory-use applications. 5) Final thoughts It was easy enough to understand the problem of unfairness, but I found it very intriguing how in the DRAM world, the term “fairness” as a solution wasn't that easy to define (which was brought to my attention in Section 4). -------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors" by Kim et al. Student reviewer: Name withheld to protect the diligent. As DRAM is getting smaller and smaller and bits are packed more densely, it leads to a problem where multiple row refreshes in the same row lead to bit flipping and errors. An experiment, testing, and solution is carried out to prove that this is a problem and that solutions do exist in modern day DRAMs. Good *Explained clearly the set up and how it was tested within the specifications of the DRAM. *Gave a short background about how DRAM works and how it is refresh and accessed. *Provided plots that show the count of errors depending on different variables such as variable RI, AI, refresh interval, and others. *Showed number of uncorrectable multi-bit errors even when using error-correction. *Explained how far the aggressor row effects other rows. *Tested on big three DRAM modules from different manufacturing times. *Gave a reliable test using simple software and FPGA further testing. Made it clear that this was an actual problem in today's DRAM modules. *Explained how some modules favored different kinds of errors while others favored errors going the opposite way. *Patterns were also tested where nearby cells can have protector cells to lower the chance of an error. *Through multiple iterations they found that PARA is the most efficient solution. They also provided other solutions such as improving circuit design, better error correctors, shorter refresh periods, and identify problem rows. *Further explains the PARA software solution and show how it is easy to add and provides clear results that PARA works without impacting much performance. *Overall the paper gave lots of clear hard evidence and data and provided some background which made it easier to understand. It then provided solutions and showed how the solution they developed was a good solution that is supported by tests and measurements. Bad *A little hard to understand without a good understanding of how DRAM works or what DRAM is. *Quite technical and is filled with lots of data that may be hard to understand although they did a good job at explaining it in simple terms. *Kind of dry and does not show they faced many challenges. Improvements *Give a better understanding to the importance of DRAM and maybe talk about challenges faced when doing the tests. Enjoyment *I enjoyed how they gave lots of data and plots and tried to make it easier to understand. -------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "RAIDR: Retention-Aware Intelligent DRAM Refresh" by Liu et al. Student reviewer: Name withheld to protect the diligent. Summary: DRAM today is refreshed every 64ms, but for most DRAM cells, 64ms is a very short time for refresh. Most cells can go for up to 256ms or more without having to be refreshed. Only a select few number of DRAM cells have to be refreshed every 64ms. Currently, and even more so in future technology, a lot of speed, energy, and time is lost by refreshing every cell every 64ms. RAIDR introduces a new way to refresh DRAM cells that causes very noticeable improvements in the three areas that I mentioned before. The general idea is to only refresh cells about as often as each individual cell needs to be refreshed. Strengths: * The paper introduces the problem of DRAM refresh taking up more resources than is necessary and how it will get worse into the future if nothing changes * The background information given about DRAM is very useful for anyone who is not very acquainted with how DRAM works * The paper addresses the way that RAIDR can be useful with different types of DRAM Weaknesses: * The mention of Bloom filters in the beginning can be confusing if you have no experience with Bloom filters * The Evaluation Methodology section may not be able to be understood by everyone Comments: DRAM is used in most computer systems in existence today. It is ubiquitous as far as I've seen, and yet it has a big downfall of the refresh required. That is the current bottleneck preventing the technology from being faster and more efficient. RAIDR introduces a low over- head, brand new way to deal with the problem of DRAM refresh. Most DRAM cells don't need to be refreshed as often as 64ms (the current time that DRAM is refreshed). Using only 1.25 KB more storage in the memory controller, RAIDR can improve the speed and efficiency of DRAM by a lot. Basically, using Bloom filters and keeping track of which cells fall into a certain “bin” of how often they need to be refreshed, you can stop every single DRAM cell from being refreshed every 64ms. Improvements: * While the paper does explain most technologies that it mentions, it could go into further detail whenever it is first mentioned as to not confuse the reader * The paper could elaborate more on potential new applications that would further increase the speed and efficiency of DRAM in conjunction with RAIDR What I thought: I learned that there is at least one easy way to get a large improvement in the use of DRAM, something that almost everyone uses every day. This paper showed me how thinking of a problem that exists in current technology and some research can really come up with new ways to solve the problem. I think the idea of RAIDR being used in memory controllers everywhere is great. If everyone were to get this benefit of higher efficiency DRAM with less time being used for refreshing cells, it would be fantastic. Now, however, is the time to think of a way to no longer have to refresh your main memory cells. -------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems" by Moscibroda and Mutlu Student reviewer: Name withheld to protect the diligent. The given paper “Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems” examines how the shift from single-core to multi-core systems has resulted in the emergence of a new type of security attack known as a Denial of Service attack (DoS) where an application can have a detrimental impact on the memory related performance of another application running on the same chip. The paper goes on to describe how such Memory Performance Hogs (MPHs) and DoS attacks come about as a result of the sharing of DRAM among processor cores and the inherent unfairness of the DRAM scheduling policy. The paper goes on to examine the performance costs for real programs running on an Intel Pentium D 930 based dual-core system and also proposes an alternative memory scheduling algorithm known as FairMem that can help mitigate the DoS attacks. ==Strengths of the paper== 1.It is able to clearly explains the root of the problem and how each of the aspects of the current memory scheduling policy : row-hit-first and oldest-first scheduling lead to unfair scheduling as they favour programs with greater row-buffer locality and greater memory request rates respectively 2. The setup of the experiments carried out to examine the performance of the MPHs are very well defined and the controlled variables such as system loading were carefully monitored. 3. The paper proposes an alternative scheduling algorithm as well as its hardware implementation and examines the improvement in performance that results from using this new scheduling algorithm on the micro benchmark applications used to show the performance hits that result from MPHs. ==Weaknesses of the paper== 1. The paper does not consider the additional costs that would arise from the addition of the new FairMem hardware to general purpose systems and also does not give an indication of the time span that would be required to introduce this new system. 2. The paper does not consider the future evolution of memory systems and how new features added may aid or obstruct the addition of new scheduling hardware. On the whole I found this paper a very interesting read as unlike most papers that examine the enormous benefits that came about through the paradigm shift to multi-core systems, it examines one of the major costs. I believe that this paper would be more convincing if it examined DoS attacks in the context of some real-world applications and discussed whether the requirements placed by those applications would require the addition of the new hardware. -------------------------------------------------------------------------------------------- NOTE: THIS IS A SAMPLE REVIEW PROVIDED BY A STUDENT. It is not an instructor's solution, but the instructor likes this review due to its overall clarity and thoroughness. Certain parts of the review, such as grammar, can certainly be improved, and the review can be made even more thorough and clear, but we are providing you this as is so that you have a good example solution in your hands that shows our expectation. -------------------------------------------------------------------------------------------- Reviewed paper: "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors" by Kim et al. Student reviewer: Name withheld to protect the diligent. =Paper Summary= In this paper, the authors expose the disturbance errors in commodity DRAM chips from recent years based on their experiments and then promoted their solution. The authors did convincing and exhaustive experiments to show that this phenomenon widely existed among commodity DRAM chips and then concluded that it was caused by the frequent toggling of a row's wordline. At last, based on their experiments results and analysis, they gave out the PARA solution. =Strengths= *This is the first paper to expose this phenomenon of disturbance errors. *They did control experiment to conclude that the disturbance errors were caused by frequent toggling of a row's wordline. *They picked three typical modules and did deeper experiments on them by using FPGA test platforms to precisely evaluate the influence of other factors, like RI, AI, and data pattern. *They not only showed their experiments results, but only provided some potential solutions and their own solution. =Weaknesses= *They could not analysis this problem in circuit level, which makes their conclusion a little unconvincing. For example, they could only hypothesize the reasons for the results of aggressor row effects. And they could not evaluate their solution on real chips. *”Often” is a key word in their conclusion. Though they gave the results that as few as 139K access would induce an error, they didn't make it further by discussing whether typical application programs would make 139K access in limited time. =My thoughts= It's an interesting paper. I'm extremely curious about what led the authors write this paper. This problem did exist since 2012. If this problem widely existed and had great influence on programs or practical applications, why there were no other related papers before theirs? Did they really meet this problem during their other research? And a detail made me confused that they said their testing platform(ML605) does not scramble the data it writes to DRAM, while in the notation they said the data is scrambled by memory controller. I searched “scramble” in Xilinx Memory Solution they mentioned in this paper and got nothing. I infer they didn't use scrambling, so the value in the cells are all '0's or '1's. However, as far as I know, scrambling is a good way to resist interference. Why didn't they use scrambling? Or why didn't they try some other data pattern rather than all '0's or '1's in a single row?