18-447 Introduction to Computer Architecture – Spring 2015

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===== Lab 5 FAQs =====

  * (Q) Do we need to update the BTB for conditional branches that have been predicated out by having the target set as PC+4 in the BTB during the execute stage as well? Or should the target be the target of the branch if it were taken? Anyone who has finished the branch predictor know this? I am failing random tests and I think its because I am updating the BTB with pc+4 for a predicated out instruction.
    * (A) You should be storing the target of the branch, as PC+4 will always be assumed should the branch not be taken.

  * (Q) Is there any way to see the debug statements that are printed when we #define DEBUG, or any printf statement? The only output I can ever get is the refsim comparison.
    * (A) You can run the simulator by itself w/o make verify

  * (Q) BTB Unconditional Bit?  Do we still need to have an unconditional bit per entry in the BTB?
    * (A) Yes

  * (Q) Are we allowed to modify the existing Pipe_Op struct provided to us?
    * (A) Yes. Everything in a file that is modifiable (should be everything except shell.*), is modifiable including the data structures.

  * (Q) Is there a change to how SWI 10 should be handled?
    * (A) Yes. The fix has been added to the starter code, but if you've already started, the change is fairly simple. Once you get a SWI 10 in the wb stage, you should set the Pipe.PC = op->pc+4 and return, not fetching anymore instructions.

  * Note: Make sure you source setup447

18-447 Introduction to Computer Architecture – Spring 2015

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