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labs [2013/02/13 21:51] yoonguk [Lab 3: Pipelined MIPS (Due: Fri. 3/1)] |
labs [2013/05/16 11:59] (current) justinme |
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| Line 6: | Line 6: | ||
| * {{lab1.pdf|Lab 1 Handout}} | * {{lab1.pdf|Lab 1 Handout}} | ||
| + | * {{lab1_dist.pdf|Lab 1 Score Distribution}} | ||
| ===== Lab 1.5: Synthesis Workflow and Verilog Register File (not due) ===== | ===== Lab 1.5: Synthesis Workflow and Verilog Register File (not due) ===== | ||
| - | |||
| * {{lab1.5.pdf|Lab 1.5 Handout}} | * {{lab1.5.pdf|Lab 1.5 Handout}} | ||
| ===== Lab 2: Single-Cycle MIPS (Due: Fri. 2/15) ===== | ===== Lab 2: Single-Cycle MIPS (Due: Fri. 2/15) ===== | ||
| - | |||
| * {{lab2.pdf|Lab 2 Handout}} | * {{lab2.pdf|Lab 2 Handout}} | ||
| + | * {{lab2_dist.pdf|Lab 2 Score Distribution}} | ||
| ===== Lab 3: Pipelined MIPS (Due: Fri. 3/1) ===== | ===== Lab 3: Pipelined MIPS (Due: Fri. 3/1) ===== | ||
| - | |||
| * {{lab3.pdf|Lab 3 Handout}} | * {{lab3.pdf|Lab 3 Handout}} | ||
| + | * {{lab3_dist.pdf|Lab 3 Score Distribution}} | ||
| + | |||
| + | =====Lab 4: Control Flow and Branch Prediction (Due: Fri. 3/22) ===== | ||
| + | * {{lab4.pdf|Lab 4 Handout}} | ||
| + | * {{lab4_dist.pdf|Lab 4 Score Distribution}} | ||
| + | |||
| + | =====Lab 5: Simulating Caches and Branch Prediction (Due: Fri. 4/5) ===== | ||
| + | * {{lab5.pdf|Lab 5 Handout}} | ||
| + | * {{lab5_dist.pdf|Lab 5 Score Distribution}} | ||
| + | |||
| + | =====Lab 6: Memory Hierarchy (Due: Wed. 4/24) ===== | ||
| + | * {{lab6.pdf|Lab 6 Handout}} | ||
| + | * {{lab6_dist.pdf|Lab 6 Score Distribution}} | ||
| + | =====Lab 7: Multicore and Cache Coherence (Due: Wed. 5/3) ===== | ||
| + | * {{lab7.pdf|Lab 7 Handout}} | ||
| + | * {{lab7_dist.pdf|Lab 7 Score Distribution}} | ||
labs.1360810264.txt.gz · Last modified: 2013/02/13 21:51 by yoonguk
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