• Please note that we do not have the resources to provide any support for the lab files and that they are provided as-is.

Lab 1: Instruction-Level MIPS Simulator (Due: Fri. 2/1)

Lab 1.5: Synthesis Workflow and Verilog Register File (not due)

Lab 2: Single-Cycle MIPS (Due: Fri. 2/15)

Lab 3: Pipelined MIPS (Due: Fri. 3/1)

Lab 4: Control Flow and Branch Prediction (Due: Fri. 3/22)

Lab 5: Simulating Caches and Branch Prediction (Due: Fri. 4/5)

Lab 6: Memory Hierarchy (Due: Wed. 4/24)

Lab 7: Multicore and Cache Coherence (Due: Wed. 5/3)