Lecture and Course Schedule

Lectures will be on Mondays and Wednesdays. Labs will be released every two weeks, and are due by the end of the Friday lab session. Please see the Main Page for lecture and lab times and locations.

In the Readings, P&P refers to Patt & Patel, “Introduction to Computing Systems: From Bits and Gates to C and Beyond.” P&H refers to Patterson and Hennessy, “Computer Organization and Design: The Hardware/Software Interface, Fourth Edition.”

Week Date Lect. # Video Topic Readings for Lecture Weekly Lab Homeworks Buzz words
1 M 1/16 No Lecture (MLK Day) No Lab Meetings (first week)
W 1/18 L1 pptpdf Intro Lab 1 Out HW 0 and HW 1 Out From Lecture 1
R 1/19 pdf MIPS ISA Tutorial
F 1/20
2 M 1/23 L2 pptpdf Fundamental Concepts and ISA Patt 2001, P&P Ch. 1, P&H Ch. 1 and 2 HW 0 Due From Lecture 2
W 1/25 L3 pptpdf ISA Tradeoffs P&P Ch. 4 From Lecture 3
F 1/27
3 M 1/30 L4 ppt pdf Video More ISA Tradeoffs and Single-Cycle Microarchitectures P&H Ch. 4.1 - 4.4, P&P Ap. C HW 1 Due Solution, HW 2 Out From Lecture 4
W 2/1 L5 ppt pdf Video Single-Cycle Microarchitectures P&P revised Appendix C, P&H Appendix D Lab 2 Out From Lecture 5
F 2/3 Lab 1 Due
4 M 2/6 L6 pptpdf Video Multi-cycle Microarchitectures From Lecture 6
W 2/8 L7 pptpdfmicrocode worksheet Video Microprogrammed Microarchitectures P&H Ch. 4.5 - 4.8 From Lecture 7
F 2/10
5 M 2/13 L8 pptpdfLDW microcode worksheet Video (HQ) Microprogramming and Pipelined Microarchitectures HW 2 Due Solution, HW 3 Out From Lecture 8
W 2/15 L9 pptpdf Video (HQ) Pipelining and Related Issues Pipelined LC-3b microarchitecture handout, Hamacher et al., Chapter 6 Lab 3 Out From Lecture 9
F 2/17 Lab 2 Due
6 M 2/20 L10 pptpdf Video Data and Control Dependence Handling in Pipelined Microarchitectures From Lecture 10
W 2/22 L11 pptpdf Video (HQ) Video (LQ) Control Flow Handling From Lecture 11
F 2/24
7 M 2/27 L12 pptpdf Video (HQ) Video (LQ) Control Flow and Exceptions P&H 4.9-4.11, Smith and Sohi 1995 HW 3 Due (Solutions on blackboard) From Lecture 12
W 2/29 L13 pptpdf Video (HQ) Video (LQ) Out-of-Order Execution Lab 4 Out HW 4 Out From Lecture 13
F 3/1 Lab 3 Due
8 M 3/5 L14 Review Session
W 3/7 Midterm 1
F 3/9
M 3/12 Spring Break
W 3/14 Spring Break
F 3/16 Spring Break
9 M 3/19 L15 pptpdf Video (HQ) Video (LQ) Approaches to Concurrency (OoO, DataFlow, Vector, VLIW) HW 4 Due Solution, HW 5 Out From Lecture 15
W 3/21 L16 ppt pdf Video (HQ) Video (LQ) Approaches to Concurrency (SIMD and VLIW) P&H 5.1-5.3, Hamacher+ 8.1-8.7, Wilkes 1965 Lab 5 Out From Lecture 16
F 3/23 Lab 4 Due
10 M 3/26 L17 ppt pdf Video (HQ) Video (LQ) Memory Hierarchy and Caches From Lecture 17
W 3/28 L18 ppt pdf Video (HQ) Video (LQ) Caches and Main Memory From Lecture 18
F 3/30
11 M 4/2 L19 ppt pdf Video (HQ) Video (LQ) Main Memory HW 5 Due Solution From Lecture 19
W 4/4 L20 ppt pdf Video (HQ) Video (LQ) Memory Scheduling and Virtual Memory Mutlu and Moscibroda ISCA'08 HW 6 Out, Lab 6 Out From Lecture 20
F 4/6 Lab 5 Due
12 M 4/9 L21 ppt pdf Video (HQ) Video (LQ), Review Session Video Virtual Memory P&H 5.4 From Lecture 21
W 4/11 Midterm 2
F 4/13
13 M 4/16 L22 ppt pdf Video (HQ) Video (LQ) Tolerating Memory Latency HW 6 Due Solution From Lecture 22
W 4/18 L23 ppt pdf Video (HQ) Video (LQ) Tolerating Memory Latency II Mutlu et al., HPCA'03 Lab 7 Out From Lecture 23
F 4/20 Lab 6 Due
14 M 4/23 L24 ppt pdf Video (HQ) Video (LQ) Runahead and Multiprocessing Amdahl, 1967; Hill et al.; Culler and Singh; P&H; Lamport From Lecture 24
W 4/25 L25 ppt pdf Video (HQ) Video (LQ) Multiprocessor Correctness and Cache Coherence From Lecture 25
F 4/27
15 M 4/30 L26 ppt pdf Video (HQ) Video (LQ) More Coherence and Interconnects From Lecture 26
W 5/2 L27 ppt pdf Video (HQ) Video (LQ) Multi-Core Potpourri HW 7 Out From Lecture 27
F 5/4 Lab 7 Due
T 5/8 Video Review session
R 5/10 Final Exam (5.30 pm - 8.30 pm) Wean 7500