Labs

We have three Lab sections. You may come to any lab section to have your lab checked off. Labs will be assigned on Wednesdays (every other week) and due on the Friday two weeks later, by the end of the Friday lab session (9:20pm).

*UPDATE*: Please see the revised policy on Lab 6 and Lab 7 deadlines at the bottom of this page.

Lab 1 (assigned Wednesday, Jan 18; due Friday, Feb 3)

Please refer to the Lab Document for a description of this lab and its deliverables.

Grading

You will check-off your lab 1 simulator in any of the three Lab Sections. When you check-off your lab, we will ask you to simulate each of the programs that is provided in the tests/ directory of the lab files, and we will compare the register file output after each test runs with a “known good” register snapshot. We have provided these register dumps for you in /afs/ece/class/ece447/labs/lab1.regdumps/ so that you can verify correct operation in exactly the same way that we will. To test, run the corresponding test program in your simulator with the “go” command, and then use “rdump” to dump the register file after the simulator halts. You should see the same values that we provide. You can use the test.sh script, present in the lab1 directory on AFS, to verify this behavior: simply copy it to your lab1 directory and run it.

Once your lab has been checked-off in person, we will test your turned-in code more extensively to ensure that all of the corner cases are correct. Your final lab grade will be based on both the in-person check-off as well as this extensive testing.

The final test cases can be found in /afs/ece/class/ece447/labs/lab1.finaltests/.

Resources

As questions arise, we will address them on the Lab 1 FAQ and Clarifications page.

The MIPS R4000 manual to which this lab refers can be found at /afs/ece/class/ece447/docs/r4000man.pdf.

The syscall which you implement in this lab (to terminate the program) is part of the set of SPIM syscalls, defined here. In a later lab we will implement the real syscall instruction (as defined by the MIPS architecture manual).

Lab 1 Grades Distribution

Lab 1.5 (Verilog Practice; No hand-in, No due date)

Please see the lab document for details.

The TAs will give short Verilog tutorials in lab in the week of Jan 30 – Feb 3 for those who are a bit rusty in Verilog.

Lab 2 (assigned Wednesday, Feb 1; due Friday, Feb 17)

Please refer to the Lab Document for a description of this lab and its deliverables.

Lab Check-Off

You will check-off your lab 2 RTL in any of the three Lab Sections. When you check-off your lab, we will ask you to show that your RTL is synthesizable with the “make synth” command, and then we will ask you to run a behavioral simulation with several test programs. We also require you to hand in a diagram of the processor's structure when checking off your lab.

Once your lab is checked off, be sure that you also place your RTL in the lab hand-in directory: /afs/ece/classes/ece447/handin/ECE-ID/lab2/.

Both of these requirements are detailed in the lab document.

Resources

As questions arise, we will address them on the Lab 2 FAQ and Clarifications page.

Lab 2 Grades Distribution

Lab 3 (assigned Wednesday, Feb 15; due Friday, Mar 2)

Please see the Lab Document.

Lab Check-Off

As before, you must check off your lab in one of the Lab Sections. We will ask you to show that your RTL is synthesizable and show that several test programs work; we will also ask you to hand in a pipeline diagram, and we will ask you to describe your pipeline design. Details can be found in the handout.

We are offering a small amount of extra credit for checking off early. We are also offering more significant extra credit and a prize for the top 3 designs judged on execution speed (critical path length multiplied by average CPI). See the handout for more details.

Resources

Lab 4 (assigned Wednesday, Feb 29; due Friday, March 23)

Please see the Lab Document.

Lab Check-Off

You must check off your lab in one of the Lab Sections. We will ask you to show that your RTL is synthesizable and show that several test programs work; we will also ask you to hand in a pipeline diagram, and we will ask you to describe your pipeline design. Details can be found in the handout.

Resources

Lab 5 (assigned Wednesday, Mar 21; due Friday, April 6)

Please see the Lab Document.

Lab Check-Off

You must check off your lab in one of the Lab Sections. We will ask you about how you implemented the required features in your simulator, and we will have you run several tests.

Resources

Please see the Lab 5 FAQ and Clarifications page.

We will give an overview of the baseline timing simulator in lab/recitation sections during the first week of the lab.

Final Test Cases

We've released the final test cases that we used to grade Lab 5 at /afs/ece/class/ece447/labs/lab5.finaltests/.

Lab 5 Grades Distribution

Lab 6 (assigned Wednesday, April 5; due Monday, April 23)

Please see the Lab Document.

Note that this lab is due on a Monday because of Carnival the previous weekend.

UPDATE: We have released a binary for the golden solution. You can debug your lab using this simulator. We will accept resubmissions with the same due date as Lab 7, but with a 20% penalty. We'll multiply your grade by 0.8 if you turn in by the new due date. No late Lab 6's will be accepted after May 6.

Please use the lab6-late handin directory for any such resubmissions.

Resources

Lab 7 (assigned Monday, April 23; due Friday, May 4)

Please see the Lab Document.

UPDATE: You can use 2 additional days without any penalty. There will be no additional late days at all after May 6.

Resources