18-447: Introduction to Computer
Architecture, Spring 2008
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Notices |
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· Go to Blackboard for the latest announcements |
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Quick Links |
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Go to
Blackboard for announcements and handouts Course Schedule and Download
Lecture Notes Archive of Lecture
Notes from the most recently completed semester A
Short Intro to Synopsys Design Compiler A
Short Intro to ModelSim Verilog Simulator |
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Course Description |
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Computer architecture is the science and art of
selecting and interconnecting hardware components to create a computer that
meets functional, performance and cost goals. This course introduces the
basic principles and hardware structures of a modern programmable computer.
We will learn, for example, how to design the control and datapath for a
pipelined RISC processor and how to design fast memory and storage systems.
The principles presented in lecture are reinforced in the laboratory through
design and simulation of a register transfer (RT) implementation of a RISC
processor pipeline in Verilog. Prerequisites: 18-240 and 15-213. |
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Staff |
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Meetings |
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Lecture: MW, 2:30 - 4:20,
DH-A310 · Lab
Section A: T, 6:30 – 8:20, HH 1107 ·
Lab Section B: R, 6:30 – 8:20, HH 1107 |
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Textbooks |
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Computer Organization and
Design: The Hardware/Software Interface, Third Edition by Patterson and Hennessy,
Morgan Kaufmann/Elsvier. (Required) ·
Also useful, textbooks from 18-240 and 15-213 |
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Office Hours |
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James Hoe, MW 4:30-5:30pm, HH-A304 Additional office hours available by
appointment ·
Yongjun Jeon, Th 5:30-6:30, HH 1107 · Tze Chang Ng, Tu 5:30-6:30, HH 1107 · Eriko
Nurvitadhi, F 11am-12pm, HH-A314 |
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Fun Links |
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·
CS
15-213 Introduction to Computer Systems ·
ECE
18-240 Fundamentals of Computer Engineering ·
ECE 18-447 Introduction
to Computer Architecture (Spring 2006 archive) ·
ECE
18-741 Advanced Computer Architecture ·
ECE
18-742 Parallel Computer Architecture ·
Computer
Architecture Lab at Carnegie Mellon (CALCM) ·
History of Computing ( ·
Microprocessor
Lineage ( ·
OpenCores
(repository of GPL hardware IPs) ·
Leon3
SPARC core (VHDL) ·
OpenSPARC
(open-sourced SPARC T1 and T2 Verilog RTL and more) |