Instructor: Office, phone: Email, URL: Office hours: Administrative Assistant: Office, phone: Email, URL: Class: Class URL: Lectures: TA: Office, phone: Email,URL: Office hours: TA: Office: Email,URL: Office hours: TA: Office: Email,URL: Office hours: TA: Office: Email: Office hours: Lab Location: Section A: Section B: Section C: Section D:

Professor Babak Falsafi HH A305, 268-7047 babak@cmu.edu, www.ece.cmu.edu/~babak Mondays 4:00pm - 5:00pm & Fridays 11:00am -12:00pm or by apppointment Matt Koeske HH A301, 268-7293 koeske@ece.cmu.edu, www.ece.cmu.edu/people/staff/koeske.html 18-347 Introduction to Computer Architecture www.ece.cmu.edu/~ece741/ Mondays & Wednesdays 2:30pm - 3:50pm BH A51 Jared Smolens HH A313, 268-7920 jsmolens+347@ece.cmu.edu, www.ece.cmu.edu/~jsmolens Wednesdays 10:30am - 11:30am & Thursdays 10:30am - 11:30am, or by appointment Ryan Ungaretti HH 1107 rju@ece.cmu.edu, www.andrew.cmu.edu/~rju Thursdays 3:00pm - 4:00pm & Fridays 2:00pm - 3:00pm, or by appointment (Friday 10/24 only: 10:00am-11:00am) Adam Kushner HH 1107 akushner@ece.cmu.edu, www.ece.cmu.edu/~akushner Mondays 5:30pm - 6:30pm & Tuesdays 1:30pm - 2:30pm, or by appointment Maneesh Sharma TBA maneeshs@andrew.cmu.edu TBA HH 1107 Mondays 6:30pm - 8:20pm Jared CANCELLED (please sign up for A, C, or D) Tuesdays 2:30pm - 4:20pm Adam Tuesdays 4:30pm - 6:20pm Ryan

Required Text: Reference Text:

Computer Organization & Design: The Hardware Software Interface by John L. Hennessy and David A. Patterson published by Morgan-Kaufmann publishers The VerilogŪ Hardware Description Language either Fourth or Fifth edition by Donald Thomas and Philip Moorby published by Kluwer Academic Publishers. This is the same book you used in 18-240.

You are responsible for all the material covered in class including the Text chapters, handouts, and class notes. If you are unable to appear for an exam for any reason, you must contact Prof. Falsafi before the exam.

There is no tolerance for academic dishonesty. Please refer to the University Policy on cheating and plagiarism. Discussion and group studies are encouraged. However, all submitted material must be the student's individual work or in case of lab assignments, the designated group's work. Example behavior that is considered academic dishonesty: writing solutions or code to assignments together copying solutions or code from any previously written solutions to a problem (e.g., solution book, prior semester's solution set, graded homeworks from prior semesters, etc.). You can talk to the professor or TAs for clarification if you have any questions.

What is computer architecture? Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course introduces the basic hardware structure of modern programmable computer. We will learn, for example, how to design the control and data path hardware for a processor in Verilog, how to make machine instructions execute simultaneously, and how to design fast memory and storage systems. Learning to design programmable systems requires that you already have the knowledge of building register transfer (RT) systems, program in assembly language as is taught in the important prerequisite 18-240. Knowledge of the behavior storage hierarchies (e.g., cache memories) and virtual memory as taught in the introduction to computer systems 15-213 is recommended. Who should take 18-347? 18-347 is the first in a series of computer architecture courses offered at Carnegie Mellon. The course is best suited for students who have completed 18-240 but also have a knowledge of computer system software and programming, and hardware description programming in Verilog. The course will include lectures, homeworks, labs and recitations. To hone the students skills in computer architecture design and implementation, the students will implement a dual-issue superscalar pipelined processor with caches and branch prediction in Verilog. The processor will implement a subset of the MIPS instruction set and run MIPS-based binaries provided as test benchmarks to completion. What knowledge does 18-347 assume? 18-347 assumes that you are familiar with the following material: Basic RT system design (18-240) Basic RT system implementation in Verilog (18-240) Basic assembly language programming (18-240) High-level languages and data structures Knowledge of memory and storage systems (15-213) recommended

All assignments will be available on the course home page. Your solutions to the assigned problems are due at the beginning of the class period on the specified due date. Prof. Falsafi does not accept late homework.

To hone the students skills in computer architecture design and implementation, the students will implement a dual-issue superscalar pipelined processor with caches and branch prediction in Verilog. The processor will implement a subset of the MIPS instruction set and run MIPS-based binaries provided as test benchmarks to completion. The project is broken down into a number of milestones (~4-5). Each milestone will be assigned as a lab assignment and will be graded separately. The final design accounts for 30% of the course grade and will include a dual-issue pipelined MIPS superscalar. A working processor with caches will receive an extra set of bonus points that will be described when the lab assignment for the final milestone is handed out. Lab assignments handed in late will lose 10% of the total lab points per day from the due date.

If there is an arithmetic error in adding the points on your assignment, see the grader immediately. You have one week from (including weekends) from the day any particular graded assignment is returned to you to appeal the grade assigned. After the one week period is up, we will not change a grade for any reason. For instance, We are going to be totally unsympathetic to students who come for regrade on Homework 2 the day before the final exam!