Corrections-Field Effect Devices and Applications, first printing

 

Edition page-the cover image should be credited to Integrated Circuit Engineering, Inc. (used with permission).

 

 

 

Chapter 4, page 124: The CIE is the Commission Internationale Éclairage.

 

 

 

 

Chapter 4, page 131, footnote 22: 10 bits=1024 levels.

 

 

 

 

Chapter 5, page 218, Figure 5.42. This figure was not reduced very well, and consequently it is difficult to read the labels in the key. In addition, this photograph does not reflect the astonishingly detailed SEM photos provided by Integrated Circuit Engineering.

 

 

Chapter 6, page 235. (both text and figure have errors). There are J row addresses (A₀-A_J-1); K-J column address bits (A_J-A_K-1); and the number of output bits is 2^N-K.

 

 

Chapter 6, page 259, Figure 6.22. This figure was not reduced very well and does not reflect the astonishingly detailed SEM photos provided by Integrated Circuit Engineering.

 

 

Chapter 7, page 296, Figure 7.29. This is entirely the wrong figure. The figure which should go here looks something like this.

 

 

 

Chapter 8, page 316, Figure 8.2a,b. The figures for enhancement mode and depletion mode devices are interchanged. Of course, the depletion mode device has no channel with zero gate bias.

 

 

Chapter 8, page 321, Fig. 8.7a. The ground for the substrate connection is missing.

 

 

 

Chapter 8, page 316, Figure 8.2a,b. The figures for enhancement mode and depletion mode devices are interchanged. Of course, the depletion mode device has no channel with zero gate bias.

 

 

Chapter 8, page 326, Equation 8.19. The upper limit on the first integral is -v_xo (not v_xo).

 

 

 

 

I hope there aren't too many more, but if you find some I'd like to hear about them.