Micro Power Management for Macro Systems on Chip

DESCRIPTION:

Increased integration of hundreds of processing cores on the same silicon substrate has allowed the concurrent execution of multiple applications on a chip, but at the cost of significant increase in on-chip power consumption. On-chip power management has therefore become a critical component of every step in the many-core design flow, from physical design all the way up to micro-architecture and system-level design. While dynamic power management has been extensively studied for the case of single-core systems, many-core systems present additional challenges that require maintaining appropriate performance levels for applications running on the system both in the context of turning on/off cores and using selectively power states, or in the context of using Dynamic Voltage Frequency Scaling (DVFS) for enabling a certain performance level at a minimum power. Furthermore, enabling power management at macroscale – for hundreds or thousands of on-chip resources – while relying on capabilities developed at microscale – specifically, technology and device-level knobs – becomes an essential for effective power control.

This workshop addresses this need by targeting emerging topics in power management and control of large scale many-core systems, such as scalability, distributed vs. centralized vs. hybrid approaches, as well as technology-driven challenges that need to be considered for providing a truly power-aware solution, such as static and dynamic variations and reliability, as well as limits for control strategies for technologies 22nm and beyond.

FINAL PROGRAM:

8:45-9:00	Introduction to the workshop (D. Marculescu, S. Lesecq)
9:00-9:45	*Keynote 1:* Technology at the design and system levels for making fine-grain dynamic power management a reality Fabien Clermidy - CEA-LETI, FR
9:45-10:30	*Keynote 2:* Fine-grained Power management for heterogeneous many-core architectures in 32nm and beyond Luca Benini - Università di Bologna & STMicroelectronics, IT
10:30-11:00	Coffee break
11:00-12:05	Power modeling and optimization *Regular papers:* An Energy Scalability Model for Efficient Resource Allocation on Manycore Architectures Joosung Kim, Hakbong Kim, Hyunhee Kim and Jihong Kim – School of Computer Science and Engineering, Seoul National University, KR Task scheduling based on energy token model Danil Sokolov and Alex Yakovlev – University of Newcastle, UK Exploiting the Correlation Between Leakage and Frequency for Speed-binning Siddharth Garg – University of Waterloo, CA *Poster highlights:* Improving Automated Stress Pattern Generation For Increasing SoC Dynamic Power Consumption Mauricio De Carvalho, Paolo Bernardi, Ernesto Sanchez and Giovanni Squillero – Politecnico di Torino, IT Enabling Timing and Power Aware Virtual Prototyping of HW/SW Systems Kim Gruettner¹, Kai Hylla¹, Sven Rosinger¹, Philipp A. Hartmann and Wolfgang Nebel² – ¹OFFIS and ²Carl von Ossietzky University Oldenburg, DE GPGPU-Accelerated Instruction Accurate and Fast Simulation of Thousand-core Platforms Shivani Raghav¹, Christian Pinto², Andrea Marongiu², Martino Ruggiero¹, David Atienza¹ and Luca Benini² – ¹Ecole Polytechnique Federale de Lausanne (EPFL) – ESL, CH and Università di Bologna – DEIS, IT
12:05-13:25	Lunch
13:25-14:30	Thermal and Power Management *Regular papers:* Fault Tollerant Thermal Management for High-Performance Multicores Andrea Bartolini, Matteo Cacciari, Alessio Cellai, Manuel Morelli, Andrea Tilli and Luca Benini – Università di Bologna – DEIS, IT System Level Power Management for Many-Core Systems Simon Holmbacka, Jens Smeds, Sébastien Lafond and Johan Lilius – Åbo Akademi University Department of Information Technologies, FI Game Theoretic Power Management Techniques for Real-Time Scheduling James Docherty and Alex Yakovlev – University of Newcastle, UK *Poster Highlights:* DVFS applied to a Homogeneous MPSoC for Power-Efficient Algorithms Implementations Roberto Airoldi, Fabio Garzia and Jari Nurmi – Tampere University of Technology, FI Energy-Aware Simultaneous Architecture Exploration and Task Scheduling for MPSoCs under Process Variation Mahboobeh Ghorbani, Mahmoud Momtazpour and Maziar Goudarzi – Sharif University of Technology, IR
14:30-15:00	Coffee Break + Poster Session (Including all papers and posters above)
15:00-15:30	Poster Session (cont’d – Including all papers and posters above)
15:30 - 16:30	*Panel Session* (Organizer: R. Marculescu) – Cutting the Gordian Knot: Power management for extreme scale computing under extreme scale constraints Panelists: Kees Goosens – Technical University Eindhoven, NL Robert Dick – University of Michigan, Ann Arbor, US Norbert Wehn – Technical University Kaiserslautern, DE Peter Feldmann – IBM TJ Watson, US

IMPORTANT DATES:

Submission deadline: Monday, November 19, 2010 (completed)

Notification of acceptance: Friday, December 3, 2010 (completed)

Final 2-page abstract version submission : Friday, February 4, 2011

A workshop digest based upon the 2-pages abstract will be distributed to all participants of the workshop. Note that the papers presented at the DATE workshops are NOT disseminated through the official DATE proceedings or through any other formal channels, such as, for example, the IEEExplore or the ACM Digital Library.

SUBMISSION: (completed)

Authors are invited to submit contributions as 2-page long abstracts. On-going works are welcome. The contribution must be submitted electronically through:

http://www.easychair.org/conferences/?conf=upm2soc10

All submissions must be written in English, and only PDF files are accepted. All 2-pages abstract must be prepared in accordance with the DATE manuscript style. All submitted 2-page abstracts will undergo the same review process (at least 2 reviews per contribution). Selected contributions will be presented in regular sessions or in a poster session. More information can be found in the Call for Contributions.