35th Annual International Symposium on Microarchitecture
Istanbul, Turkey, Nov.18-22, 2002

Tutorial on Partially Asynchronous Microprocessors (PAMs)

Diana Marculescu (CMU), Dave Albonesi (U. of Rochester), Pradip Bose (IBM), and Alper Buyuktosunoglu (IBM/U. of Rochester)


· Intended Audience

This tutorial is intended to provide industry and university-based computer architects and processors designers with an overview of partially asynchronous systems and the impact of such a design style on processor performance and power consumption.

· Abstract

This tutorial addresses the problem of Partially Asynchronous Microprocessor (PAM) design. Partially Asynchronous systems include Globally Asynchronous Locally Synchronous (GALS) systems, and Locally Asynchronous Globally Synchronous (LAGS) systems, which are two examples of intermediate design styles between fully synchronous and fully asynchronous. GALS systems contain several independent synchronous blocks which operate with their own local clocks and communicate asynchronously with each other. The main feature of these systems is the absence of a global timing reference and the use of several distinct local clocks (or clock domains), possibly running at different frequencies. In the case of high-end core processors, global clock distribution issues are perhaps the best motivating factor for the study of GALS systems: with each technology shrink, the clock distribution network of a large chip grows rapidly in complexity and requires large design effort, power consumption and die area.

On the other hand, LAGS systems have locally self-timed modules embedded within a fully synchronous design. Such design approaches are suitable in cases where power efficiency is important, as is the case of power consuming resources such as floating point units.

As opposed to fully synchronous processors, PAMs offer the advantage of fine-grain control of local clock speeds and voltages, thus providing additional power savings capabilities, under a wide variety of applications and workloads.

Tutorial Schedule

 
· Part I
o Trends and issues in clock distribution.

o How much asynchrony do we want?

o Motivation for GALS, synchronization issues, deadlock prevention, possible inter-clocking domain communication schemes.

o GALS processors: microarchitectural organization and power/performance evaluation.

· Break

· Part II

o GALS processors: power/performance evaluation (cont’d).
o Workload characterization and impact on the use of fine grain speed/voltage scaling.

· Part III

o Case study - LPX, an IPCMOS based LAGS processor
· Part IV
o Looking in the crystal ball: Where will partially asynchronous design style be used?

o Concluding remarks
· Q&A
 

Presenters' Bios


Diana Marculescu is an Assistant Professor of ECE at Carnegie Mellon University. She has received her Ph.D. in Computer Engineering in 1998 from University of Southern California and her M.S. in Computer Science from "Politehnica" University of Bucharest in 1991. After spending 2 years at University of Maryland, Dr. Marculescu has joined Carnegie Mellon University where she is currently leading the Energy Aware Computing (EnyAC) group focusing on techniques and tools for enabling synergistic hardware/software power management and novel paradigms for energy-delay efficient computing. Diana Marculescu is a recipient of a National Science Foundation CAREER Award (2000-2004) and a member of the organizing committee of the ACM/IEEE International Symposium on Low Power Electronics and Design. She also serves on the technical program committee of several conferences, including IEEE/ACM International Conference on Computer-Aided Design and IEEE Design, Automation and Test in Europe Conference. Her research interests are in the area of energy aware computing, VLSI, computer architecture and CAD for power modeling and estimation.

David H. Albonesi is an Associate Professor of Electrical and Computer Engineering at the University of Rochester and Co-Director of the Advanced Computer Architecture Laboratory. He received his B.S.E.E. from the University of Massachusetts Amherst in 1982, his M.S.E.E. from Syracuse University in 1986, and his Ph.D. in Electrical and Computer Engineering from the University of Massachusetts Amherst in 1996. Prior to receiving his Ph.D., he held technical and management leadership positions for 10 years at IBM Corporation (1982-86) and Prime Computer, Incorporated (1986-1992). The primary focus of his industry work was on the design, implementation, and debugging of low-latency, high-bandwidth memory hierarchies for high performance processors, the development of shared memory multiprocessor systems, and the development and application of architectural evaluation, design implementation, and hardware emulation tools. At Rochester, he leads the Complexity-Adaptive Processing (CAP) project and is also conducting research in understanding and improving dynamic branch prediction, multithreaded architectures, and VLIW architectures for voice and video applications. Dr. Albonesi received a National Science Foundation CAREER Award and IBM Faculty Partnership Awards in 2001 and 2002.

Alper Buyuktosunoglu received B.S. degree in Electrical and Electronics Engineering, from Middle East Technical University, Ankara, Turkey in 1998, with the honors, and M.S. degree in Electrical and Computer Engineering from University of Rochester, Rochester, New York, in 1999. He is pursuing his Ph.D. degree at University of Rochester. He is currently a research engineer at IBM T. J. Watson Research Center. His research interests include: high performance, low power computer architectures and digital microelectronic design. He is a member of the IEEE.

Pradip Bose received his B.Tech degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 1977 and the M.S. and Ph.D degrees in Electrical and Computer Engineering from the University of Illinois, Urbana-Champaign, in 1981 and 1983 respectively. Since May 1983, Dr. Bose has been a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. During this time, Dr. Bose has conducted research projects that led to well-known IBM products such as RS/6000 and POWER3. Between 1989-1990 he has led the UNDP (United Nations Development Program) funded program to establish a Center for Advanced Research on Fifth Generation Computer Systems at Indian Statistical Institute (ISI), Calcutta, India, as part of his assignment as a Visiting Associate Professor at ISI. His current research interests include: high performance, low power computer architectures and their performance evaluation, verification and testing. Dr. Bose has over 60 refereed publications and is the author of a book by MIT Press (to appear in late 2002). He is active in many conference committees and is a senior member of IEEE; in 2001-2002, he was Program Chair of IEEE Int'l. Symp. on Performance Analysis of Systems and Software (ISPASS), and he is a member of the program committees of MICRO-35 and HPCA-9. His most recent conference tutorials include offerings (with other co-speakers) at ISCA-2001, HPCA-2001 and Sigmetrics-2001.