Tutorial on Partially Asynchronous Microprocessors (PAMs)
June 8, 2003
30th Annual International Symposium on Computer Architecture
San Diego, California, USA
June 9-11, 2003
Diana Marculescu (CMU), Dave
Albonesi (U. of Rochester), Pradip
Bose (IBM), and Alper Buyuktosunoglu (IBM/U. of Rochester)
· Intended Audience
This tutorial is intended to provide industry and university-based computer
architects and processors designers with an overview of partially
asynchronous systems and the impact of such a design style on processor
performance and power consumption.
· Abstract
This tutorial addresses the problem of Partially Asynchronous
Microprocessor (PAM) design. Partially Asynchronous systems include Globally Asynchronous Locally
Synchronous (GALS) systems, and Locally Asynchronous Globally
Synchronous (LAGS) systems, which are two examples of intermediate
design styles between fully synchronous and fully asynchronous.
GALS systems
contain several independent synchronous blocks which operate with their own
local clocks and communicate asynchronously with each other. The main
feature of these systems is the absence of a global timing reference and
the use of several distinct local clocks (or clock domains), possibly
running at different frequencies. In the case of high-end core processors,
global clock distribution issues are perhaps the best motivating factor for
the study of GALS systems: with each technology shrink, the clock
distribution network of a large chip grows rapidly in complexity and
requires large design effort, power consumption and die area.
On the other hand, LAGS systems have locally self-timed modules embedded
within a fully synchronous design. Such design approaches are suitable in
cases where power efficiency is important, as is the case of power
consuming resources such as floating point units.
As opposed to fully synchronous processors, PAMs offer the advantage of
fine-grain control of local clock speeds and voltages, thus providing
additional power savings capabilities, under a wide variety of applications
and workloads.
o Trends and issues in clock distribution.
o How much asynchrony do we want?
o Motivation for GALS, synchronization issues, deadlock prevention, possible inter-clocking domain communication schemes.
o GALS processors: microarchitectural organization and power/performance evaluation.
· Part II
o GALS processors: power/performance evaluation (cont’d).
o Workload characterization and impact on the use of fine grain speed/voltage scaling.
· Part III
o Case study - LPX, an IPCMOS based LAGS processor· Part IV
o Looking in the crystal ball: Where will partially asynchronous design style be used?· Q&A
o Concluding remarks