Dr. Rasit Onur Topaloglu GlobalFoundries

Sub-50 nm and 3D-IC Design and Manufacturability Challenges and Solutions

Manufacturability for semiconductor integrated circuits presents many challenges in upcoming technologies in 22 nm and 32 nm. One such challenge is due to utilization of double patterning lithography (DPL). DPL is a technique that is used to print devices and interconnects with smaller pitches. Dr. Topaloglu is going to analyze the device and interconnect aspects of this method and tie it to variability in circuits. Furthermore with 3D integration, there will be topographic challenges which may cause yield and variability. Dr. Topaloglu is going to present his recent research in this area to mitigate and optimize for such effects and manufacturability challenges. Depending on audience interest and interaction, Dr. Topaloglu will also present recent research on device contact resistance impact on design. University collaboration opportunities will furthermore be discussed.

Bio:

Dr. Rasit Onur Topaloglu received his B.S. degree with High Honors in Electrical and Electronic Engineering from Bogazici University in Turkey. He received his M.S. degree in Computer Science and Ph.D. degree in Computer Engineering from University of California at San Diego. Since 2005, he has been with Advanced Micro Devices, which recently spun off its manufacturing section under the name GlobalFoundries as an advanced semiconductor manufacturer with technology coverage down to 28 nm and research down to 15 nm. Dr. Topaloglu’s research interests are design for manufacturability, VLSI design automation, high performance computing, and nanoelectronics. He has over 30 international and refereed publications, four book chapters that are to be published this year, one granted and three pending patents, and a best paper award at IEEE International Symposium on Quality Electronic Design.