Automatic Pipeline Synthesis from Transactional Datapath Specifications
Pipelining is a classic and widely used microarchitectural performance optimization. Pipelining is often necessary to meet performance targets and improve efficiency. For example, in the instruction processor market, the majority of commercial processors are pipelined, with forwarding and speculation support.
Unfortunately, pipelining a datapath by hand is tedious and error prone, as it requires the designer to reason about subtle corner cases when sequentially dependent operations are processed concurrently by different pipeline stages. Adding pipeline optimizations such as forwarding and speculation further exacerbates the problem.
This talk will present the transactional datapath specification (T-spec) and the technology (T-piper) to synthesize automatically an in-order pipelined implementation from it. T-spec abstractly views a datapath as executing one transaction at a time, computing next system states based on current ones. From a T-spec, T-piper can synthesize a pipelined implementation that preserves the original transactional semantics, while allowing concurrent execution of multiple overlapped transactions across pipeline stages. Furthermore, T-piper supports the commonly used forwarding and speculation pipeline optimizations.
We have made T-piper available online at www.t-piper.net. The talk will include a brief demonstration of automatic pipelining using this online version of T-piper. Finally, we will also present the results from case studies in applying T-spec and T-piper in MIPS and x86 processor pipeline development.
Eriko Nurvitadhi is currently a PhD candidate in the Electrical and Computer Engineering Department at Carnegie Mellon University, advised by Prof. James C. Hoe. He received BSs, BA, MS, and MBA degrees from Oregon State University. His research interests include microarchitecture design automation and FPGA-based emulation.