|
Deming Chen
University of Illinois |
New Design Techniques for Existing and Futuristic FPGAs
As cost and complexity for ASIC designs grow in a steady and rapid pace along the technology scaling, FPGA designs offer an attractive alternative. In this talk, I will mainly present two recent research results on FPGAs generated at University of Illinois. The first targets existing FPGAs for performance optimization using a novel BDD (binary decision graph)-based synthesis paradigm. We use a technique called linear expansion for BDD decomposition, which in turn enables a dynamic programming algorithm to efficiently search through the optimization space for the BDD. The second work targets a futuristic CNT (carbon nanotube)-based FPGA architecture named FPCNA. We define novel CNT and nanoswitch-based components and characterize these components considering nano-specific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physical-design flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. At the end of the talk, I will also briefly introduce some other research activities we carried out recently, including a CUDA-to-FPGA design flow and variation-aware high-level synthesis.
Dr. Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He worked as a software engineer between 1995-1999 and 2001-2002. He has been an assistant professor in the ECE department of University of Illinois, Urbana-Champaign since 2005. He is a research assistant professor in the Coordinated Science Laboratory and an affiliate assistant professor in the CS department. His current research interests include nano-systems design and nano-centric CAD techniques, FPGA synthesis and physical design, high-level synthesis, microarchitecture and SoC design under parameter variation, and reconfigurable computing.
|
