Carnegie Mellon University
On the Mitigation of NBTI-Induced Performance Degradation
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal reliability concerns in nanoscale designs. As technology scaling proceeds aggressively (e.g., thinner gate oxide without proportional downscaling of supply voltage and higher operating temperature due to higher power density), the rate of NBTI-induced performance degradation is getting faster. Experiments on PMOS aging indicate that NBTI can incur a 50mV increase in the magnitude of PMOS threshold voltage, and in turn slow down the circuit by nearly 10%. If the thickness of gate oxide shrinks down to 4nm, the circuit lifetime will be dominated by NBTI.
In this talk, I will present a novel framework using joint logic restructuring (LR) and pin reordering (PR) to mitigate NBTI-induced performance degradation. Based on detecting functional symmetries and exploring transistor stacking effects, the proposed methodology involves only wire perturbation and introduces no gate area overhead. These two approaches are synergistic and poised to provide potential benefits for each other. Experiments reveal that the joint LR and PR framework successfully recovers benchmark circuits from performance degradation with minimum cost. In addition, the recovered circuits have fewer critical transistors still under severe NBTI, leading to low overhead for post-processing transistor resizing.
Kai-Chiang Wu received his B.S. and M.S. degrees both in Computer Science from National Tsing Hua University, Taiwan, in 2002 and 2004. He is currently a Ph.D. student in Electrical & Computer Engineering at Carnegie Mellon University, advised by Prof. Diana Marculescu. His research interests include logic synthesis and optimization for circuit reliability in nanoscale designs and emerging technologies.