Carnegie Mellon University
Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale IC
As the feature size of integrated circuits continues to scale down, parametric variation of manufacturing process becomes increasingly difficult to control, causing great uncertainty in circuit behavior. To
understand and combat process variations, silicon testing and characterization is an important infrastructure that facilitates many statistical IC design techniques, such as statistical timing analysis, post-silicon tuning, etc. However, most
traditional silicon characterization approaches are extremely expensive: Hundreds of test structures must be deployed in wafer scribe lines and/or product chips to capture spatial variations.
In this talk, I will present a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor the wafer/chip-level parametric variation of manufacturing processes and/or
circuit performances. VP exploits recent breakthroughs in sparse linear regression to recover nearly complete statistics from remarkably small sample sets. Moreover, an optimal sampling strategy is derived from Bayesian inference and information
theory to determine the optimal sampling locations where test structures should be deployed and measured to monitor spatial variations with maximum accuracy. Our industrial examples with silicon measurement data demonstrate that VP reduces the
estimation error by up to 10x compared to the traditional methods.
Wangyang Zhang received his B.S. and M.S. degrees in Computer Science from Tsinghua University, in 2006 and 2008 respectively. He is currently a Ph.D. student in the department of Electrical and Computer Engineering
at Carnegie Mellon University, where he is advised by Prof. Xin Li and Prof. Rob Rutenbar. His research interests include efficient statistical methods for VLSI CAD under process variations.