Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, March 17, 12:00-1:00 p.m. HH-1112


Natasa Miskov-Zivanov
Natasa Miskov-Zivanov
Carnegie Mellon University

Probabilistic Modeling and Optimization for Circuit Reliability

Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the increase in transistor integration capacity to implement complex systems also leads to the increase in process variations. Despite these difficulties, it is expected that systems remain reliable while delivering the required performance. Reliability and variability are emerging as new design challenges, thus pointing to the importance of modeling and analysis of transient faults and variation sources for the purpose of guiding the design process.

In this talk, I will present a probabilistic and symbolic modeling approach for efficient and accurate evaluation of the impact of transient faults on combinational and sequential circuits. The proposed approach allows for the analysis of circuits from different aspects: the susceptibility of individual outputs, state lines and the overall circuit to transient faults, as well as the impact of individual gates and flip-flops on circuit fault susceptibility. The developed symbolic model also allows for the analysis of multiple transients, the statistical analysis of transient fault propagation when process parameter variations are considered and the implementation of transient fault protection techniques.


Natasa Miskov-Zivanov is a postdoctoral research associate in the Electrical and Computer Engineering Department at Carnegie Mellon University. She received her Ph.D. degree and M.S. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2008 and 2005, respectively, and a B.S. degree in Electrical Engineering and Computer Science from University of Novi Sad, Serbia, in 2003. Her current research focuses on reliability analysis and fault-tolerance in nanoscale designs