Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, November 24, 12:00-1:00 p.m. HH-1112


Yen-Tzu Lin
Yen-Tzu Lin
Carnegie Mellon University

Test Effectiveness Evaluation through Analysis of Readily-Available Tester Data

Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. In this talk, I will introduce a general test-metric evaluation methodology that exploits the readily-available test-measurement data in chip-faliure log files. The methodology provides a cost-effective approach for analyzing the effectiveness of new and existing test and DFT methods, and does not require the generation and application of new test patterns. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) physically-aware-N-detect, (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).


Yen-Tzu Lin is currently a Ph.D. candidate in Electrical and Computer Engineering at Carnegie Mellon University, advised by Professor Shawn Blaton. She recieved her B.S. and M.S. degrees in Electrical Engineering from National Tsing Hua University, Taiwan, in 2000 and 2002 respectively. Her research interests include VLSI test methodology development, evaluation, and efficiency improvement through utilization of GPUs.