Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, April 21, 12:00-1:00 p.m. HH-1112


Gokce Keskin
Gokce Keskin
Carnegie Mellon University

Statistical Element Selection

Increasing variability in modern CMOS processes is a major challenge for analog circuit designs that rely on precise matching of components (e.g. op-amps, current sources, capacitors). Although systematic variations can be significantly reduced by regular circuit layouts, random variations such as dopant fluctuations and line edge roughness are much more difficult to overcome. In this work, we exploit increasing random variability by using small components (e.g. transistors) and selecting a subset among them that satisfies a given specification (Statistical Element Selection). We develop a generalized yield modeling methodology to decide between tradeoffs (size and number of selectable elements, and configuration time) for a given design. We compare the results with traditional approaches and explore the use of the methodology for a range of applications.


Gokce Keskin got his B.S. degree in Electical Engineering from Bilkent University, Turkey in 2003. He graduated from the ECE department at Carnegie Mellon in December '05. He worked in high speed data links at Intel Corporation during 2006. He started the Ph.D. program in 2007 at Carnegie Mellon. His primary interests are in analog, RF and mixed signal circuits.