Variation-Aware Path Test Using Statistical Timing
Meeting the tight performance specifications mandated by the customer is critical for contract-manufactured ASICs. To address this, at-speed test has been employed to detect subtle delay failures in manufacturing.
However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the presence of process variation is difficult because the critical path is no longer unique. Different paths become frequency limiting in different process corners.
In this talk, I present a novel variation-aware method based on statistical timing to select critical paths for structural test. Node criticalities are computed to determine the probabilities of different circuit nodes being on the critical path across process variation. Experimental results for multimillion gate ASICs demonstrate the effectiveness of the method.
Vikram Iyengar joined IBM in July 2002 as Advisory Engineer in ASICs Test Methodology. His current research is focused on at-speed structural test and low-DPM test of advanced-nanometer designs.
Dr. Iyengar is a recipient of the Boston University ECE Chair Fellowship Award, the IBM Graduate Fellowship Award, the European Design Automation Association's Outstanding PhD Dissertation Award, and several IBM Patent File Awards.
Dr. Iyengar is serving as Program Chair of the IEEE North Atlantic Test Workshop 2008-2009.
Dr. Iyengar received the BE degree from the Birla Institute of Technology, India in 1996, the MS degree from Boston University in 1998, and the PhD degree from Duke University in 2002, all in Computer Engineering.