Carnegie Mellon University
Time-Interleaved C-2C SAR ADCs For High-Speed Medium-Resolution Applications
High-speed (>GSamples/sec) medium-resolution (6-8 bits) Analog-to-Digital Converters (ADC) are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. However, due to complex DSP and low-power constraints, digital basebands are generally designed in low-leakage, high-VT low power (LP) digital CMOS processes. Since the ADC has to be on the same die with the digital baseband for cost reduction purposes, this makes the design of high-speed ADCs very challenging. The ADC should not only meet the constraints but also should be scalable due to the possible future applications. Successive Approximation Register (SAR) based ADCs have become very popular over the last decade because of their highly scalable, digital friendly, and power-efficient architecture and steady improvement in the matching and density of capacitors. In general, SAR ADCs are medium-speed architectures and cannot achieve >GSamples/sec sampling rate but they are ideally suited for time-interleaving where multiple ADCs work in parallel to boost the overall speed. Even though many ADCs can be necessary to meet the speed constraint, the overall topology can still be more efficient than a design with similar specifications implemented with a single ADC.
This talk focuses on the design of a 2.5GSamples/sec, Nyquist, 7-bit Time-Interleaved C-2C SAR ADC implemented in a 45nm LP Digital CMOS process which consumes 50mW from a 1.1V supply. 16 ADCs were used to achieve the overall 2.5GSamples/sec sampling rate and several calibration schemes are implemented to enhance the performance. Best to our knowledge, this ADC is the first 7-bit ADC implemented in a digital 45nm CMOS process achieving this speed.
Erkan Alpman received his B.S. and M.S. degrees in 2003 and 2005, respectively, from the Middle East Technical University (METU), Ankara Turkey, in Electrical and Electronics Engineering. His M.S. Thesis was awarded as "METU Thesis of The Year" in 2006. He has been pursuing his PhD degree in Electrical and Computer Engineering in the Carnegie Mellon University, Pittsburgh PA since 2006 under the supervision of Prof. L. Richard Carley. From 2007 to 2008, he was a full-time intern at Intel Corporation, Hillsboro, OR. His research interests include high-speed ADCs in sub-100nm digital CMOS and RF circuits for WLAN transceivers.