Kai-Chiang Wu Carnegie Mellon University

Circuit Optimization Techniques for Radiation-Induced Soft Errors

Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors). Logical masking, electrical masking, and latching-window masking, which prevent transient events in logic circuits from being latched into memory elements, are weakened with continuous scaling trends. Therefore, soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits.

In this talk, I will present two frameworks for soft error rate (SER) reduction. The first one, based on redundancy addition and removal (RAR), estimates the effects of redundancy manipulations and accepts only those with positive impact on SER. Several metrics and constraints are introduced to guide RAR towards SER reduction in an efficient manner. The second framework, based on selective voltage scaling, assigns a higher supply voltage (V_DD ^H) to gates that have large error impact and contribute most to the overall SER. The number of V_DD ^H -gates, highly associated with the power overhead, can be bounded by the use of level converters. These two techniques are orthogonal and can thus provide additive improvements to each other.

Bio

Kai-Chiang Wu received his B.S. and M.S. degrees both in Computer Science from National Tsing Hua University, Taiwan, in 2002 and 2004. He is currently a Ph.D. candidate in Electrical & Computer Engineering at Carnegie Mellon University, advised by Prof. Diana Marculescu. His research interests include logic synthesis and optimization for circuit reliability in nanoscale designs and emerging technologies.